Abstract: The sense circuit includes first and second inverters connected at their inputs to a signal input node and a reference node, respectively. The inverters are selectively biased to different quiescent points for charging the signal input node and the reference node to different quiescent voltage levels. Signals applied to the signal input and reference nodes cause the potential at these nodes to vary from their quiescent values. The inverters are selectively cross-coupled to form a flip flop whose binary value is determined by the outputs of the inverters. For the same value of signals applied to the two nodes the flip flop is set to the state dictated by the initial voltage offset due to the difference in the quiescent points of the inverters.

Abstract: The sense circuit includes first and second inverters, connected at their inputs to first and second nodes, respectively. The inverters are selectively cross-coupled by means of transmission gates whose conduction paths are connected between the output of the first and second inverters, respectively, and the inputs of the second and first inverters, respectively. The control electrodes of the transmission gates are coupled to the first and second nodes whereby the transmission gates are turned on and off in response to the voltage levels at the first and second nodes. In the operation of the circuit a precharge voltage, having a polarity and magnitude to turn off the transmission gates, is applied to the two nodes. Subsequently, first and second current signals, having a polarity to generate potentials to turn on the transmission gates, are applied to the first and second nodes, respectively, altering the potentials at the nodes until the transmission gates are turned on.

Abstract: A circuit for generating a logic function and its logical complement of N binary variables utilizing MOS transistors which are all of the same conductivity type. The circuit may include an N input NAND gate comprising N MOS transistors and a load element, the conduction paths of the transistors connected in series with the load element to form a first series circuit and an inverter circuit having N+1 MOS transistors, the conduction paths of which are connected in series to form a second series circuit. Each series circuit is connected between the same operating voltage terminals and the two are interconnected to one another in such manner that the power dissipation of the circuit compares favorably with a CMOS inverter.