Patents by Inventor Richard John Stephani
Richard John Stephani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9753667Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.Type: GrantFiled: March 10, 2015Date of Patent: September 5, 2017Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Travis Hebig, Myron Buer, Carl Monzel, Richard John Stephani
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Publication number: 20160246506Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.Type: ApplicationFiled: March 10, 2015Publication date: August 25, 2016Inventors: Travis HEBIG, Myron BUER, Carl MONZEL, Richard John STEPHANI
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Patent number: 8787099Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.Type: GrantFiled: June 20, 2012Date of Patent: July 22, 2014Assignee: LSI CorporationInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Richard John Stephani, Christopher David Sonnek
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Patent number: 8773927Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.Type: GrantFiled: September 7, 2012Date of Patent: July 8, 2014Assignee: LSI CorporationInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Richard John Stephani, Bijan Kumar Ghosh, Ronald Brian Steele
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Publication number: 20140071775Abstract: A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: LSI CorporationInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Richard John Stephani, Bijan Kumar Ghosh, Ronald Brian Steele
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Publication number: 20130343139Abstract: A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: LSI CorporationInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Richard John Stephani, Christopher David Sonnek
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Patent number: 8462562Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.Type: GrantFiled: November 18, 2011Date of Patent: June 11, 2013Assignee: LSI CorporationInventors: Ankur Goel, Donald Albert Evans, Dennis Edward Dudeck, Richard John Stephani, Ronald James Wozniak, Dharmendra Kumar Rai, Rasoju Veerabadra Chary, Jeffrey Charles Herbert
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Publication number: 20130128676Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: LSI CORPORATIONInventors: Ankur Goel, Donald Albert Evans, Dennis Edward Dudeck, Richard John Stephani, Ronald James Wozniak, Dharmendra Kumar Rai, Rasoju Veerabadra Chary, Jeffrey Charles Herbert