Abstract: The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled.

Abstract: A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.

Abstract: A time division multiplexing (TDM) method and apparatus for interfacing data channels with a TDM bus. The TDM interface uses a processor and a channel coordinator circuit to indicate which data channels are active, and to assign which TDM transmit channels and which TDM receive channels will correspond to the active data channels. The processor controls the flow of data by using a channel coordinator circuit which controls multiple shift registers. The multiple shift registers control the flow of data between the active channels and the TDM bus. Multiple storage registers are used to buffer the data flowing between the active channels and the shift registers.

Abstract: The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled.

Abstract: An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit.