Patents by Inventor Richard Joseph Noreika

Richard Joseph Noreika has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6664794
    Abstract: A test vehicle for an SIR testing system is described. A circuit board having a plurality of interleaved circuit patterns is provided with replica components mounted thereon. The interleaved circuit patterns have different conductor spacings to permit a qualitative evaluation of electronic assembly manufacturing processes. The replica components have connection leads which are soldered to circuit pads on the circuit board. The circuit pads are connected into two groups which are used along with the interleaved circuit patterns to evaluate the manufacturing process using SIR measurements.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Charles David Fieselman, Richard Joseph Noreika, Joseph Donald Poole
  • Patent number: 6326797
    Abstract: A test coupon for measuring the effects of solder processes on circuit testability. The test coupon includes a circuit board having a multiplicity of circuit conductor patterns. Each conductor pattern is connected to a plurality of pads and vias on the circuit board. The circuit pads on an opposite surface of the circuit board support solder connections to a plurality of different circuit components. The circuit pads are connected to the vias, which in turn are connected to individual conductors of the circuit pattern. A surface connector is also supported on the circuit board, having pins extending through the circuit board. The circuit pattern conductors terminate on a respective connector pin. The test coupon may be subject to in-circuit testing where a value of the various components are measured. The multiple circuit patterns and mounted components permit different types of tester pins to be used to evaluate in-circuit testability in a test coupon used in a particular manufacturing process.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: December 4, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ray J. Caggiano, Boyd H. Furr, Jeff A. Hatley, Richard Joseph Noreika
  • Patent number: 6054720
    Abstract: A test vehicle for an SIR testing system is described. A circuit board having a plurality of interleaved circuit patterns is provided with replica components mounted thereon. The interleaved circuit patterns have different conductor spacings to permit a qualitative evaluation of electronic assembly manufacturing processes. The replica components have connection leads which are soldered to circuit pads on the circuit board. The circuit pads are connected into two groups which are used along with the interleaved circuit patterns to evaluate the manufacturing process using SIR measurements.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Charles David Fieselman, Richard Joseph Noreika, Joseph Donald Poole
  • Patent number: 5669137
    Abstract: An electronic package assembly wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (e.g., printed circuit board). The assembly's projecting conductive leads are soldered. An encapsulant material (e.g., polymer resin) is used to provide reinforcement for the solder-lead connections, the encapsulant material being dispensed only along opposing sides of the package's housing which do not include projecting leads (and which are oriented substantially normal to the stresses imposed on the package during operation wherein high temperatures are attained). This dispensing may follow solder reflow and solidification. The invention is particularly useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: September 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: James Vernon Ellerson, Richard Joseph Noreika, Jack Arthur Varcoe