Abstract: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.

Abstract: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.

Abstract: In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

Abstract: A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.