Abstract: A data strip (2) of predetermined size is made (a) by determining the total nibbles of digital information to be encoded and the maximum number of integral nibbles per data line (14), using predetermined minimum dibit dimensions, after allowing for parity checks, alignment guides (32,36), and a start line (28), (b) by increasing the dibit dimensions to achieve the predetermined size, and adjusting the bit size to account for ink spread, and (c) by preparing a reader instruction header (16) containing coded specifications as to the data strip format. These factors are interdependent and must be correlated to provide a final data strip (2) satisfying all the predetermined criteria.An associated printer (64) prints the data strip (2) with a header (16) and a data portion (12) in the determined format.

Abstract: A data strip (2) of predetermined size is made (a) by determining the total nibbles of digital information to be encoded and the maximum number of integral nibbles per data line (14), using predetermined minimum dibit dimensions, after allowing for parity checks, alignment guides (32,36), and a start line (28), (b) by increasing the dibit dimensions to achieve the predetermined size, and adjusting the bit size to account for ink spread, and (c) by preparing a reader instruction header (16) containing coded specifications as to the data strip format. These factors are interdependent and must be correlated to provide a final data strip (2) satisfying all the predetermined criteria.An associated printer (64) prints the data strip (2) with a header (16) and a data portion (12) in the determined format.

Abstract: A memory system for use in a video game system or the like that has a limited number of signal lines for communicating address signals and a data bus, includes random access memory (RAM) to augment that contained in the game console in addition to plural segments of read only memory (ROM). A first decoding circuit is coupled to the data bus and to the signal lines that communicate address signals to the ROM segments, and in response to detection of a predetermined address and a predetermined status of selected data lines produces a signal that selects one of the plurality of ROM segments of memory locations. A second decoding circuit is coupled to a selected group of the address signal lines, and also to a segment of the memory unit set aside for random access memory (RAM) to which the others of the address signal lines are also coupled.