Abstract: A computer program product for incorporating state machine controls into existing non-state machine environments includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining a state machine representation for an existing environment, assigning state indicators to each state of the state machine, transcoding existing software flags of the environment into modifier values associated with the state indicators, assigning state values based on the modifier values and the state indicators, assigning event identifiers for transitions from the state values, and creating a tabular representation of the determined state machine, the tabular representation providing next state information based on the event identifiers and the state values.

Abstract: A computer program product, apparatus and method for providing a performance neutral heartbeat in a computer communication system, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including maintaining a send flag, maintaining a receive flag, determining that a heartbeat timer has activated, checking a state of the send flag to determine if packets have been sent since a prior heartbeat timer activation and checking a state of the receive flag to determine if packets have been received since a prior heartbeat timer activation.

Abstract: A computer program product for subnet management in virtual host channel adapter topologies includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a request to add a new logical host channel adapter (HCA) to the subnet, updating a logical switch port topology control block to reflect a pointer to the new logical HCA, and updating a port topology control block of the logical HCA to reflect a pointer to the logical switch port.

Abstract: A computer program product, apparatus and method for managing recovery of a link in a multi-tasking multi-processor environment. An exemplary embodiment includes shutting off timers for a failed channel associated with the communications link, storing a loss of link condition in a data structure, disabling communications on the failed channel and sending an external notification of the loss of link condition.

Abstract: A computer program product, apparatus and method for emulating channels in a multi-tasking multi-processor environment, including identifying a plurality of physical channels having an associated physical channel identifier for each of the plurality of physical channels, associating an emulated channel from a plurality of emulated channels for each of the plurality of physical channels, thereby generating a plurality of emulated channels, each of the plurality of emulated channels having a virtual channel identifier, mapping the plurality of emulated channels on a communications link, thereby generating an emulated channel path for each of the plurality of emulated channels, defining a queue pair link buffer from a plurality of queue pair link buffers for each of the emulated channels and increasing a number of queue pair link buffers.

Abstract: A computer program product, apparatus and method for negating initiative for select entries from a shared, strictly FIFO initiative queue in a multi-tasking multi-processor environment. An exemplary embodiment includes a computer program product for negating initiative for select entries from a shared initiative queue in a multi-tasking multi-processor environment, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including identifying an element within the environment that has failed and recovered, not removing the element from the shared initiative queue and entering a boundary element entry into the shared initiative queue.

Abstract: A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.

Abstract: A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.

Abstract: A technique for establishing a logical path between two servers in a coordinated timing network of a processing environment is provided. The technique includes the exchange of command and response message pairs by a server and an attached server, via a physical link. The server transmits a command message to an attached server to establish a server-time-protocol (STP) logical path and receives a response from the attached server. The technique also includes the server receiving a request transmitted by the attached server to establish an STP logical path to the server and transmitting a response to the attached server's request. A logical path between the server and the attached server is established if the attached server's response indicates that the server's request was accepted by the attached server and if the server's response indicates that the attached server's request was accepted by the server.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: An information processing system is provided which includes an interrupt table including a plurality of entries relating to interrupts requested by entries in a plurality of event queues. The entries of the interrupt table reference identifiers, and the identifiers are assigned to events from a pool of identifiers in accordance with an order in which the events occur.

Abstract: A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with the definition(s) of the z/Architecture; and wherein a process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.

Abstract: A method for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then issued requesting the communications interface to virtualize the communication port. In response to the second command, one or more virtual switches are then configured to connect to the communication port, each virtual switch including a plurality of virtual ports, such that the one or more virtual switches are configured in a manner sufficient to support the number of images of virtual ports indicated by the obtained information. Thereafter, upon request via issuance of a third command, a logical link is established between one of the virtual ports of one of the virtual switches and a communicating element of the information handling system.

Abstract: A method of managing memory mapped input output operations to an alternate address space comprising: executing a first instruction directed to a first memory mapped input output alternate address space of a machine associated with a first adapter to allocate a resource associated with the first adapter to a process in accordance with a definition of a z/Architecture; wherein a selected process issues at least one of a load and a store instruction executed in a problem state of the machine to a selected address location of a selected resource. The method further includes ensuring that the selected resource corresponds with the allocated resource and determining that the selected process corresponds with the process to which the resource is allocated.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: A method and apparatus that provide connectivity in a computer network environment that includes a plurality of nodes, interface links and at least one central electronic complex divided into one or more physical and or virtual sub-environments. A first control program is provided in the central electronic complex in order to establish a first command process layer and a first transfer process layer within this first control program for handling data. The first command process layer is then linked to the first transfer process layer in this control program. A second control program is also provided in the central electronic complex in order to establish a second command process layer and a second transfer process layer within this second control program for handling data. The second command process layer is also linked to the second transfer layer in said second control program.