Patents by Inventor Richard K. Hester
Richard K. Hester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8749215Abstract: Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge that reduces ripple current or variations in the inductor current by adjusting phase relationships between corresponding buck and boost switches in a bridge or buck-boost mode.Type: GrantFiled: August 31, 2010Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventor: Richard K. Hester
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Patent number: 8415937Abstract: Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.Type: GrantFiled: August 31, 2010Date of Patent: April 9, 2013Assignee: Texas Instruments IncorporatedInventor: Richard K. Hester
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Patent number: 8269475Abstract: A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.Type: GrantFiled: February 17, 2009Date of Patent: September 18, 2012Assignee: Texas Instruments IncorporatedInventors: Richard K. Hester, Patrick P. Siniscalchi
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Publication number: 20120049818Abstract: Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: Texas Instruments IncorporatedInventor: Richard K. Hester
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Publication number: 20120049816Abstract: Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge that reduces ripple current or variations in the inductor current by adjusting phase relationships between corresponding buck and boost switches in a bridge or buck-boost mode.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: Texas Instruments IncorporatedInventor: Richard K. Hester
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Patent number: 8013677Abstract: One-sided pulse width modulated (PWM) amplifiers are disclosed.Type: GrantFiled: December 16, 2009Date of Patent: September 6, 2011Assignee: Texas Instruments IncorporatedInventors: Cetin Kaya, Richard K. Hester
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Publication number: 20110140774Abstract: One-sided pulse width modulated (PWM) amplifiers are disclosed.Type: ApplicationFiled: December 16, 2009Publication date: June 16, 2011Inventors: Cetin Kaya, Richard K. Hester
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Publication number: 20100207592Abstract: A class DH amplifier is provided. The amplifier is generally comprised of a tracking power supply, a class D amplifier section, and a carrier generator. The tracking power supply receives a supply voltage and an analog input signal, and the tracking power supply provides an input for the carrier generator. Based on its input from the tracking power supply, the carrier generator can output a positive ramp signal and a negative ramp signal to the class D amplifier section. The class D amplifier section can generate an output signal base on the analog input signal and the ramp signals from the carrier generator.Type: ApplicationFiled: February 17, 2009Publication date: August 19, 2010Applicant: Texas Instruments IncorporatedInventors: Richard K. Hester, Patrick P. Siniscalchi
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Patent number: 6925171Abstract: A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260).Type: GrantFiled: May 30, 2002Date of Patent: August 2, 2005Assignee: Texas Instruments IncorporatedInventors: Minsheng Wang, Richard K. Hester
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Patent number: 6904145Abstract: The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.Type: GrantFiled: September 21, 2001Date of Patent: June 7, 2005Assignee: Texas Instruments IncorporatedInventors: Patrick P. Siniscalchi, Richard K. Hester, Donald C. Richardson, Glenn H. Westphal
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Patent number: 6803811Abstract: A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.Type: GrantFiled: October 26, 2002Date of Patent: October 12, 2004Assignee: Texas Instruments IncorporatedInventor: Richard K. Hester
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Publication number: 20040041624Abstract: A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.Type: ApplicationFiled: October 26, 2002Publication date: March 4, 2004Inventor: Richard K. Hester
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Publication number: 20020191638Abstract: A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260).Type: ApplicationFiled: May 30, 2002Publication date: December 19, 2002Inventors: Minsheng Wang, Richard K. Hester
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Publication number: 20020039413Abstract: The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.Type: ApplicationFiled: September 21, 2001Publication date: April 4, 2002Inventors: Patrick P. Siniscalchi, Richard K. Hester, Donald C. Richardson, Glenn H. Westphal
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Patent number: 5920275Abstract: A charge redistribution analog-to-digital converter uses an interpolative comparator to determine multiple bits in a single comparator decision cycle. The result is a speed improvement in the conversion period with little or no increase in power dissipation.Type: GrantFiled: September 9, 1997Date of Patent: July 6, 1999Assignee: Iowa State University Research Foundation, Inc.Inventor: Richard K. Hester
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Patent number: 5235335Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.Type: GrantFiled: June 2, 1992Date of Patent: August 10, 1993Assignee: Texas Instruments IncorporatedInventors: Richard K. Hester, Khen-Sang Tan, Michiel de Wit
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Patent number: 5038143Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.Type: GrantFiled: May 11, 1989Date of Patent: August 6, 1991Assignee: Texas Instruments IncorporatedInventor: Richard K. Hester
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Patent number: 4975700Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.Type: GrantFiled: March 21, 1990Date of Patent: December 4, 1990Assignee: Texas Instruments, IncorporatedInventors: Khen-Sang Tan, Richard K. Hester, John W. Fattaruso
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Patent number: 4903022Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The digital signal processor determines whether the sampling rate of the D-to-A and A-to-D converters is correct for the rate at which the data is being received by the respective converters. If not, the DSP sends a number of master clock cycles to the system which then retards or advances the sampling rate of the converter by that number of clock cycles.Type: GrantFiled: December 9, 1987Date of Patent: February 20, 1990Assignee: Texas Instruments IncorporatedInventors: Richard K. Hester, Nuboru Shiwaku
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Patent number: 4855743Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.Type: GrantFiled: December 9, 1987Date of Patent: August 8, 1989Assignee: Texas Instruments IncorporatedInventor: Richard K. Hester