Abstract: A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.

Abstract: A method of specification of the routing of signal and planar power nets between terminals of a core module and pads in an array of pads surrounding the core module. The method identifies proximity terminals and cyclic constraints and then routes the signal nets and power nets in separate moat rings that are concentric with the core module. The proximity terminals and any pads involved in cyclic constraints are routed in respective proximity and cyclic moat rings, adjacent the core module and pad array, respectively. Finally, the resulting moat signal nets are promoted within the signal to the next most outwardly adjacent, unoccupied concentric tracks, and then sections of the proximity, signal, power, and cyclic rings are collapsed to the next most radially inward, unoccupied concentric tracks.