Patents by Inventor Richard K. Sita
Richard K. Sita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8566382Abstract: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.Type: GrantFiled: September 8, 2009Date of Patent: October 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Larry Pearlstein, Richard K. Sita
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Patent number: 8467528Abstract: A system on a chip including a bus, a bootup module coupled to the bus and configured to cause the system on a chip to bootup in accordance with a selected security mode, an input module coupled to the bus and configured to receive an input signal and to provide the input signal to the bus, a processor coupled to the bus and configured to process the input signal to provide an intermediate signal, in accordance with a type of content protection associated with the input signal, an encryption module coupled to the bus and configured to cause at least a portion of the intermediate signal to be encrypted to produce an encrypted signal, in accordance with the type of the content protection, and an output module coupled to the bus and configured to output the encrypted signal.Type: GrantFiled: August 30, 2007Date of Patent: June 18, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Richard K. Sita, Kunal K. Dave, Jitesh Arora, Michael J. Erwin
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Patent number: 8306122Abstract: A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.Type: GrantFiled: June 23, 2008Date of Patent: November 6, 2012Assignee: Broadcom CorporationInventors: Larry Pearlstein, Richard K. Sita
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Patent number: 8225063Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.Type: GrantFiled: June 8, 2009Date of Patent: July 17, 2012Assignee: ATI Technologies ULCInventor: Richard K. Sita
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Patent number: 7898547Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.Type: GrantFiled: January 26, 2007Date of Patent: March 1, 2011Assignee: Broadcom CorporationInventors: Chun Wang, Youjing Zhang, Richard K. Sita, Glen T. McDonnell, Babs L. Carter
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Publication number: 20100077176Abstract: Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.Type: ApplicationFiled: September 8, 2009Publication date: March 25, 2010Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Larry Pearlstein, Richard K. Sita
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Publication number: 20090316041Abstract: A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.Type: ApplicationFiled: June 23, 2008Publication date: December 24, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Larry Pearlstein, Richard K. Sita
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Publication number: 20090254699Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.Type: ApplicationFiled: June 8, 2009Publication date: October 8, 2009Applicant: ATI TECHNOLOGIES INC.Inventor: Richard K. Sita
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Patent number: 7558933Abstract: A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.Type: GrantFiled: December 24, 2003Date of Patent: July 7, 2009Assignee: ATI Technologies Inc.Inventor: Richard K. Sita
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Publication number: 20080168266Abstract: A system on a chip including a bus, a bootup module coupled to the bus and configured to cause the system on a chip to bootup in accordance with a selected security mode, an input module coupled to the bus and configured to receive an input signal and to provide the input signal to the bus, a processor coupled to the bus and configured to process the input signal to provide an intermediate signal, in accordance with a type of content protection associated with the input signal, an encryption module coupled to the bus and configured to cause at least a portion of the intermediate signal to be encrypted to produce an encrypted signal, in accordance with the type of the content protection, and an output module coupled to the bus and configured to output the encrypted signal.Type: ApplicationFiled: August 30, 2007Publication date: July 10, 2008Inventors: Richard K. Sita, Kunal K. Dave, Jitesh Arora, Michael J. Erwin
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Patent number: 7253818Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.Type: GrantFiled: August 7, 2001Date of Patent: August 7, 2007Assignee: ATI Technologies, Inc.Inventors: Chun Wang, Youjing Zhang, Richard K. Sita, Glen T. McDonnell, Babs L. Carter
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Patent number: 7016418Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.Type: GrantFiled: August 7, 2001Date of Patent: March 21, 2006Assignee: ATI Technologies, Inc.Inventors: Chun Wang, Paul Chow, Richard K. Sita, Philip L. Swan
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Patent number: 6918047Abstract: A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.Type: GrantFiled: September 7, 2000Date of Patent: July 12, 2005Assignee: ATI International, SrlInventors: Richard K. Sita, Carl Mizuyabu, Oleg Drapkin
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Publication number: 20030030644Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Inventors: Chun Wang, Youjing Zhang, Richard K. Sita, Glen T. McDonnell, Babs L. Carter
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Publication number: 20030031258Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Inventors: Chun Wang, Paul Chow, Richard K. Sita, Philip L. Swan
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Patent number: 4561027Abstract: A magnetic recording system transmits data edge information and clock signals through a rotary transformer. From the signals derived from secondary side of the transformer the data is reconstructed from the edge information and retimed using the clock signals. A record amplifier is D.C. coupled to a recording head for good pulse response. The amplifier can be a differential one with a pulsed current source for still better pulse edge response.Type: GrantFiled: March 21, 1983Date of Patent: December 24, 1985Assignee: RCA CorporationInventors: Richard K. Sita, John R. Orr, John L. Waring