Abstract: A plurality of CML integrated circuit chips with input and output gates connected in a circular access linkage loop output-to-input with each chip having an interface mechanism comprising an interface register and a bypass arrangement between the input gate and the output gate so that information may flow from a transmitter output gate to a receiver input gate uni-directionally, (clockwise or counter-clockwise) through the loop by means of the bypass with minimal delay.Utilizing this circular access linkage loop together with a junction box, a number of access loops can be joined together to increase the number of chips which can be linked together.Also disclosed is a multiplexing scheme utilizing the circular access linkage loop for increasing the gate per pin ratio and for higher speed communication between chips.

Abstract: A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e., not connected to any other conductor, may be located within a shot distance, i.e., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories.

Abstract: A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e., not connected to any other conductor, may be located within a short distance, i.e., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories.

Abstract: A high speed circuit for converting CML/ECL gate signals to TTL gate signals. The circuit includes two parallel current paths coupled to a current mirror section in which uniform current is maintained in portions of each path. Each current path includes a transistor which is coupled to the CML/ECL gate for sensing the differential voltage in the gate. The TTL gate is coupled to one of the current paths which steer current into or out of the TTL gate depending upon the differential voltage sensed in the CML/ECL gate.