Patents by Inventor Richard Kenneth Oxland
Richard Kenneth Oxland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10861933Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.Type: GrantFiled: November 2, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY., LTD.Inventors: Richard Kenneth Oxland, Blandine Duriez, Mark van Dal, Martin Christopher Holland
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Patent number: 10522621Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.Type: GrantFiled: March 29, 2019Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Richard Kenneth Oxland
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Patent number: 10510853Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.Type: GrantFiled: December 18, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
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Publication number: 20190229186Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventor: Richard Kenneth OXLAND
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Publication number: 20190131413Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.Type: ApplicationFiled: December 18, 2018Publication date: May 2, 2019Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
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Patent number: 10276660Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.Type: GrantFiled: February 14, 2018Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Richard Kenneth Oxland
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Publication number: 20190074355Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.Type: ApplicationFiled: November 2, 2018Publication date: March 7, 2019Inventors: Richard Kenneth Oxland, Blandine Duriez, Mark Van Dal, Martin Christopher Holland
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Patent number: 10164024Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.Type: GrantFiled: June 22, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
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Patent number: 10164031Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.Type: GrantFiled: November 21, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
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Patent number: 10121858Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.Type: GrantFiled: October 30, 2015Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Richard Kenneth Oxland, Blandine Duriez, Mark van Dal, Martin Christopher Holland
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Patent number: 10049946Abstract: A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.Type: GrantFiled: October 17, 2016Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Richard Kenneth Oxland
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Publication number: 20180174821Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Inventor: Richard Kenneth OXLAND
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Patent number: 9911599Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.Type: GrantFiled: October 6, 2016Date of Patent: March 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Richard Kenneth Oxland
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Patent number: 9887272Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.Type: GrantFiled: December 30, 2015Date of Patent: February 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
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Patent number: 9768263Abstract: A fin field effect transistor (FinFET) device includes a substrate and a template material over the substrate. The template material absorbs lattice mismatches with the substrate. The FinFET device also includes a barrier material over the template material. The barrier material is free of point defects. The FinFET device further includes a channel material over the barrier material.Type: GrantFiled: April 13, 2016Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Christopher Holland, Matthias Passlack, Richard Kenneth Oxland
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Patent number: 9685514Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.Type: GrantFiled: October 29, 2015Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Richard Kenneth Oxland, Mark van Dal
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Patent number: 9680027Abstract: A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors.Type: GrantFiled: March 7, 2012Date of Patent: June 13, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Richard Kenneth Oxland, Mark van Dal
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Publication number: 20170125518Abstract: According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Richard Kenneth Oxland, Blandine Duriez, Mark van Dal, Martin Christopher Holland
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Publication number: 20170069728Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Inventors: Georgios Vellianitis, Mark van Dal, Blandine Duriez, Richard Kenneth Oxland
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Patent number: 9590084Abstract: A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel includes a source-side channel portion adjoining the source region, wherein the source-side channel portion has a first bandgap, and a drain-side channel portion adjoining the drain region. The drain-side channel portion has a second bandgap different from the first bandgap.Type: GrantFiled: November 26, 2014Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Richard Kenneth Oxland