Patents by Inventor Richard Kimoto

Richard Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Impedance compensated electrostatic discharge circuit for protection of high-speed interfaces and method of using the same
    Patent number: 8351170
    Abstract: The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jeffrey C. Dunnihoo, Richard Kimoto
  • Method and apparatus of providing 2-stage ESD protection for high-speed interfaces
    Patent number: 8254071
    Abstract: The present invention relates to a method and apparatus of providing 2-stage ESD protection for high-speed interfaces. An aspect of the present invention is to provide an integrated multi-stage ESD/EOS protection solution for such high-speed applications. In one embodiment, the ESD protection device has multiple ESD stages integrated into a single integrated circuit package and is mounted to a printed circuit board in series with a device under protection. In another embodiment the multiple ESD stages integrated into a single integrated circuit package of the ESD protection device are coupled with a series element that isolates a 2nd stage from a 1st stage during an ESD event, thus ensuring that the 2nd stage turns on before the 1st stage, as well as provides for less current in the 2nd stage.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: August 28, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jeff Dunnihoo, Richard Kimoto
  • IMPEDANCE COMPENSATED ESD CIRCUIT FOR PROTECTION FOR HIGH-SPEED INTERFACES AND METHOD OF USING THE SAME
    Publication number: 20090154038
    Abstract: The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 18, 2009
    Inventors: Jeffrey C. Dunnihoo, Richard Kimoto
  • METHOD AND APPARATUS OF PROVIDING 2-STAGE ESD PROTECTION FOR HIGH-SPEED INTERFACES
    Publication number: 20090046401
    Abstract: The present invention relates to a method and apparatus of providing 2-stage ESD protection for high-speed interfaces. An aspect of the present invention is to provide an integrated multi-stage ESD/EOS protection solution for such high-speed applications. In one embodiment, the ESD protection device has multiple ESD stages integrated into a single integrated circuit package and is mounted to a printed circuit board in series with a device under protection. In another embodiment the multiple ESD stages integrated into a single integrated circuit package of the ESD protection device are coupled with a series element that isolates a 2nd stage from a 1st stage during an ESD event, thus ensuring that the 2nd stage turns on before the 1st stage, as well as provides for less current in the 2nd stage.
    Type: Application
    Filed: July 25, 2008
    Publication date: February 19, 2009
    Inventors: Jeff Dunnihoo, Richard Kimoto