Abstract: Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof.

Abstract: Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof.

Abstract: A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Abstract: A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Abstract: Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.

Abstract: Systems and methods for reduced distortion in a class D amplifier are provided. An “ideal” digital output signal is produced. The “ideal” digital output signal is then compared to the actual output signal in an error amplifier. The integrator input is the difference between the output stage waveform and the ideal output stage waveform. The net input to the integrator now comprises the imperfections of the power stage, and the feedback loop drives their average to zero. This error is then amplified and integrated. The integrated signal is than applied to a summer where it is added to the analog input. Then as in the typical Class D amplifier, the integrated signal is compared in an error amplifier to a ramp signal generated from the ramp generator.

Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.

Abstract: Systems and methods are described herein for changing the frequency response of a filter, such as a hybrid circuit. One or more tunable components are adjustable to provide the hybrid circuit with a frequency response corresponding to the characteristics of an associated communications network, such as a digital subscriber link.

Abstract: The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal (12) being transmitted by the line driver (20) requires it as determined by a comparator (18). Advantageously, this reduces the power dissipation in the line driver (10) by operating the line amplifier (20) the majority of the time from the lower supply voltage. A delay circuit (14) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.

Abstract: The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply voltages, and from a higher set of voltages only when the amplitude of the signal (12) being transmitted by the line driver (20) requires it as determined by a comparator (18). Advantageously, this reduces the power dissipation in the line driver (10) by operating the line amplifier (20) the majority of the time from the lower supply voltage. A delay circuit (14) delays the signal to be amplified sufficient to allow the transitioning of the power supply voltages provided to the amplifier hysteresis of this power supply voltage switching may also be used to further reduce power dissipation.

Abstract: A system (100) for calibrating data converters (101) includes a data converter (101) that receives an input signal and generates one or more pre-digital error correction codes from the input signal. A calibrator (150) receives the pre-digital error correction codes, formulating one or more transition voltage expressions using the pre-digital error correction codes, and compares the transition voltage expressions to one or more measured transition voltage values to generate one or more calibrated values. More specifically, the data converter (101) may be a pipelined analog-to-digital converter (101).

Abstract: This document describes a simple modification to the traditional pipelined analog-to-digital converter (ADC) architecture that reduces the signal swing of the inter-stage amplifier by a factor of two. This is a significant advantage when low power supply voltages limit the output range of operational amplifies. The modification requires no additional hardware and produces no additional power consumption.

Abstract: An integrated circuit for analog to digital conversion using a plurality of unit capacitors (201). The value of each unit capacitor (201) has a nonlinear spatial component determined by the location of the unit capacitor (201) on the integrated circuit. A plurality of array capacitors (101a-101e) are formed from the unit capacitors (201) such that each array capacitor (101a-101e) includes a selected group of unit capacitors (201). The unit capacitors (201) that make up each array capacitor (101a-101e) are selected based upon the nonlinear spatial component in the unit capacitance value.

Abstract: Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.