Abstract: A burst error limiting symbol detector system includes a symbol detector circuit responsive to a corrected sample signal for detecting multilevel or multidimensional symbols encoded in the corrected sample signal with reference to a plurality of associated thresholds. A feedback equalizer circuit provides a feedback equalizer signal for cancelling undesired distortion in an input signal. A summing circuit is responsive to the input signal and the feedback equalizer signal to provide the corrected sample signal to the symbol detector circuit. A feedback modification circuit is responsive to the corrected sample being within one of a plurality of valid symbol windows to feed back the detected symbol to the feedback equalizer and is responsive to the corrected sample being within one of plurality of marginal threshold windows to feed back a corresponding intermediate value to the feedback equalizer.

Abstract: Systems and methods for augmenting the performance of iterative soft decision-in soft decision-out decoding of block codes with extrinsic information based on multiple parity equations inherent to the block codes. Cyclic shifting of codewords may be applied in the context of iterative soft decision-in soft decision-out decoding to maximize the usefulness of a parity equation corresponding to any particular codeword bit. Soft decisions are determined on a bit-by-bit basis in response to multi-bit symbol measurements. This allows the use of relatively inexpensive bit-based decoders for decoding of multi-bit symbols.

Abstract: Systems and methods for augmenting the performance of iterative soft decision-in soft decision-out decoding of block codes with extrinsic information based on multiple parity equations inherent to the block codes. Cyclic shifting of codewords may be applied in the context of iterative soft decision-in soft decision-out decoding to maximize the usefulness of a parity equation corresponding to any particular codeword bit. Soft decisions are determined on a bit-by-bit basis in response to multi-bit symbol measurements. This allows the use of relatively inexpensive bit-based decoders for decoding of multi-bit symbols.

Abstract: Improvements to amplitude phased keyed digital communications systems and to the processing of amplitude phase keyed symbols transmitted over radio frequency channels. The present invention provides for an amplitude phased keyed digital communications system including an adaptive baseband equalizer, a digital symbol recovery circuit in accordance with the present invention, and a quadrature demodulator. The adaptive baseband equalizer receives amplitude phased keyed signals and outputs in-phase and quadrature digital amplitude values corresponding to the received amplitude phased keyed signals. The digital symbol recovery circuit comprises a programmable addressable random access memory that stores a plurality of eight bit words comprising decoded symbol sets of the received amplitude phased keyed signals, and outputs the decoded symbol sets in response to addresses corresponding to the in-phase and quadrature output signals.

Abstract: An equalizer that mitigates both linear and nonlinear distortions for amplitude phase keyed signals that are processed thereby. Algorithms employed in the equalizer are based on correcting received signals based on symbol transitions between successive symbols. The linear portion of the equalizer is programmable and can use any available algorithm. Programmable linear taps of the equalizer may be programmed in a nonlinear manner by using the lookup tables as amplitude dependent equalizers that are used to process one symbol at a time. In the equalizer, each amplitude level has it's own correction factor by using amplitude dependent coefficients. The equalizer can implement both linear and nonlinear equalization. Equalizer corrections are implemented using predetermined values stored in lookup tables. The equalization corrections are determined in an external computer and are loaded into the lookup tables for each amplitude level of the received signals.

Abstract: An equalizer employed with a receiver for cancelling an interfering signal due to low cross-polarization isolation. The present equalizer provides a simple and inexpensive cross-polarization interference cancellation system. The equalizer uses an error signal generated in a residual carrier detector to determine the magnitude of an interfering signal and inputs a cancelling signal to the co-polarized channel until power in the error signal is minimized. In the equalizer, the determination of the magnitude of the interfering signal is performed at baseband (after demodulation but prior to data detection) and the cancellation is performed at RF, prior to dispersive microwave elements. In the receiver, co- and cross-polarized signals are received and amplified. A copy of the cross channel input signal is supplied to each receiver channel. An RF vector modulator is used to control the phase and amplitude of the cross-polarized signal prior to summation with a desired co-polarized signal.

Abstract: A decoder for selected linear error correcting codes, such as a BCH code, uses relatively low-speed circuitry to determine syndromes and corresponding error locations for correcting the code. In a specific embodiment of a BCH linear cyclic invariant error correcting code, only cyclic invariants are stored in Read Only Memory such that the storage requirements of the Read Only Memory are minimized, and table look-up techniques are employed to speed apparent computation. In another specific embodiment of a linear error correcting codes, a Read Only Memory is used to store precomputed indicia of possible errors in the code word, and table look-up techniques are employed to determine one or more syndromes. The table look-up method avoids the complexity of error locating polynomials, algebraic root finders and real-time computation while reducing computation time.