Abstract: A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, a combined schedule is created by pipelined staging of multicast and unicast scheduling. Multicast cells are scheduled for transmission among multiple interfaces of a crossbar by performing a multicast cell scheduling cycle for multiple classes of service that are supported by the network device. Then, unicast cells are scheduled for transmission among the interfaces at a lower priority than the previously scheduled multicast cells by performing a unicast cell scheduling cycle for the multiple classes of service using only those interfaces that remain unmatched after completion of the multicast cell scheduling cycle.

Abstract: A method performs a radix search data structure. The method selects a reference table based on a value of a selectable parameter. The reference table includes at least one of a valid reference table and a transition reference table, and contains a set of data bits. The method receives a key containing a set of data bits. The method indexes the reference table using at least a subset of data bits in the key. The method determines a result index based on at least a subset of data bits in the reference table. The method then indexes a result table based on the result index to reference a result of a radix search data structure.

Abstract: A method and apparatus are provided for scheduling multicast data in an input-queued network device. A fabric arbiter receives a transmit request associated with multiple input ports. The transmit request identifies those of the output ports to which pending multicast cells are ready to be transmitted, if any. The fabric arbiter receives a backpressure signal from a backpressuring output port. Then, based upon the backpressure signal the fabric arbiter schedules multicast cells for transmission across the fabric. If the size of a multicast queue exceeds a predetermined threshold, then the fabric arbiter ignores the backpressure signal and causes the head-of-line multicast cell from the multicast queue to be transferred to the backpressuring output port.

Abstract: A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, deterministic and bounded delay for high priority multicast cells is guaranteed by the multicast scheduler. The scheduler receives a transmit request associated with each of a plurality of input ports. The transmit request identifies output ports to which pending multicast cells are ready to be transmitted, if any. Then, for each of multiple classes of service, the scheduler performs a single scheduling iteration. The single scheduling iteration includes a grant phase, an accept phase, and an update phase. During the grant phase, the scheduler grants one or more of the input ports access to the fabric by issuing grants based upon the transmit requests and a priority indicator that identifies an input port that is given scheduling priority for the scheduling iteration.

Abstract: An apparatus and method for storage of memory packets with a high aggregate bandwidth is disclosed. An odd-even memory bank structure effectively doubles the memory available for packet storage. A packet memory arbitration scheme aligns access of devices reading and writing into packet memory allowing full-rate access to the packet memory.

Abstract: A method performs a radix search data structure. The method receives a key containing a set of data bits. The method determines a reference index based on a first subset of data bits in the key. The method indexes a reference table based on the reference index to locate a reference field. The method determines a result index based on a second subset of data bits in the key and the reference field. The method then indexes a result table based on the result index to locate a result of a radix search data structure.

Abstract: A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, multicast scheduling is triggered by a programmable parameter. Each scheduling timeslot of a set of possible scheduling timeslots, unicast cell scheduling is performed. Multicast cell scheduling is performed in parallel with and independent of the unicast cell scheduling during scheduling timeslots in which a programmable multicast scheduling frequency parameter satisfies a predetermined condition.

Abstract: A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, deterministic and bounded delay for high priority multicast cells is guaranteed by the multicast scheduler. The scheduler receives a transmit request associated with each of a plurality of input ports. The transmit request identifies output ports to which pending multicast cells are ready to be transmitted, if any. Then, for each of multiple classes of service, the scheduler performs a single scheduling iteration. The single scheduling iteration includes a grant phase, an accept phase, and an update phase. During the grant phase, the scheduler grants one or more of the input ports access to the fabric by issuing grants based upon the transmit requests and a priority indicator that identifies an input port that is given scheduling priority for the scheduling iteration.

Abstract: A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, the head-of-line blocking problem is avoided for multicast queues. A fabric arbiter receives a transmit request associated with multiple input ports. The transmit request identifies those of the output ports to which pending multicast cells are ready to be transmitted, if any. The fabric arbiter receives a backpressure signal from a backpressuring output port. Then, based upon the backpressure signal the fabric arbiter schedules multicast cells for transmission across the fabric. If the size of a multicast queue exceeds a predetermined threshold, then the fabric arbiter ignores the backpressure signal and causes the head-of-line multicast cell from the multicast queue to be transferred to the backpressuring output port.

Abstract: A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, a combined schedule is created by pipelined staging of multicast and unicast scheduling. Multicast cells are scheduled for transmission among multiple interfaces of a crossbar by performing a multicast cell scheduling cycle for multiple classes of service that are supported by the network device. Then, unicast cells are scheduled for transmission among the interfaces at a lower priority than the previously scheduled multicast cells by performing a unicast cell scheduling cycle for the multiple classes of service using only those interfaces that remain unmatched after completion of the multicast cell scheduling cycle.

Abstract: A method and apparatus are provided for scheduling unicast and multicast data in an input-queued network device. According to one aspect of the present invention, a combined schedule is created by pipelined staging of multicast and unicast scheduling. Multicast cells are scheduled for transmission among multiple interfaces of a crossbar by performing a multicast cell scheduling cycle for multiple classes of service that are supported by the network device. Then, unicast cells are scheduled for transmission among the interfaces at a lower priority than the previously scheduled multicast cells by performing a unicast cell scheduling cycle for the multiple classes of service using only those interfaces that remain unmatched after completion of the multicast cell scheduling cycle.

Abstract: The present invention is a method and apparatus for interconnection system. A first front connector is located at a side of a first front card to provide first contacts for first signal traces on the first front card. A second front connector located at a side of a second front card to provide second contacts for second signal traces on the second front card. A mating connector has first and second receptacles and is located alongside of a rear card. The mating connector electrically connects the first contacts of the first signal traces to the second contacts of the second signal traces via contacts in the first and second receptacles. The first and second receptacles couple to the first and second front connectors, respectively. The rear card is positioned in a substantially orthogonal direction to the first and second front cards.

Abstract: A method for handling cache misses in a computer system. A prefetch unit fetches an instruction for execution by one of a plurality of coprocessors. When the preferred embodiment of the present invention experiences a cache miss in a prefetch unit, the process for which an instruction is being fetched is passed off to a memory processor which executes a read of the missing cache line in memory. While the process is executing in memory processor, or queued by the scheduler for execution of the same instruction, the prefetch unit continues to dispatch other processes from the its queue to the other processors. Thus, the computer system, including the processors, do not stall. Processors continue to execute processes. The prefetch unit continues to dispatch processes. When the memory read is completed, the process in which the cache miss occurred is rescheduled by the scheduler. The prefetch again attempts to fetch and decode the instruction and arguments.

Abstract: A method and apparatus for maintaining an order of processing data packets. One embodiment of the invention includes a first stage of data packet processing, which sequentially receives a plurality of independent data packets. The data packet are to be processed at the first stage in parallel. The plurality of independent data packets are then permitted to continue processing at a separate stage only in the order the independent data packets were received at the first stage of the data packet processing. In one embodiment, the invention includes assigning a sequence number to a first independent data packet of the plurality of packets prior to the first stage of data packet processing. Thereafter, the invention includes comparing the sequence number assigned to the first independent data packet to a servicing number.

Abstract: A computer system architecture in which each processor has its own memory, strategically distributed along the stages of an execution pipeline of the processor, to provide fast access to often used information, such as the contents of the address and data registers, the program counter, etc. Memory storage is strategically located in close physical proximity to a stage in an execution pipeline at which memory is commonly or repeatedly accessed. Coupled to the pipeline at various stages are small memory cells for storing information that is consistently and repeatedly requested at that stage in the execution pipeline. The speed of the execution pipeline in a processor is critical to overall performance of the processor and the computer architecture of the present invention as a whole. To that end, the clock cycle time at which the pipeline is operated is increased as much as the operating characteristics of the logic and associated circuitry will allow.

Abstract: A method for searching for keys of arbitrary width in a table in a memory of a computer system by repeatedly executing lookup instructions on a lookup processor. The lookup processor executes a lookup instruction to find a key in a table. The execution of the lookup instruction results in a key being found, or a key not being found. If the key is not found, the process is requeued by a scheduler with the program counter register for the process pointing to the instruction immediately following the lookup instruction, i.e., the next instruction. In the event the key is found in the table, the entry in the table associated with the key contains the memory address of the next instruction to be executed. This memory address is loaded into the program counter register associated with the process in which the lookup instruction was executed. The scheduler requeues the process, later dequeues it, and the instruction pointed to by the program counter register is fetched by an instruction fetch unit.

Abstract: In a search method for a radix search tree, a logic circuit for computing the actual offset of an entry in a node in a tree. The logic circuit accepts a pointer to a node in the tree, along with an associated bit mask indicating which entries are present in the node. The logic circuit further receives an entry value, the offset of which from the beginning of the node is to be computed by the logic circuit. The logic circuit utilizes Boolean AND gates to mask off higher order bits in the bit mask above the bit position corresponding to the entry value received by the logic circuit. The lower order bits in the bit mask, up to but not including the bit position corresponding to the entry value, are added together to determine the number of entries that exist at a lower offset in the node than the entry indicated by the entry value. The logic circuit combines the pointer received with the sum computed to calculate the offset memory address at which the entry is located in the node.

Abstract: A computer implemented method for searching for a key in a radix search tree in a memory of a computer system. A table of keys is organized in a radix search tree stored in a memory of a computer system. The keys are divided into a string of symbols. Each node in the tree corresponds to a symbol. A path from a root node to a leaf node at level n in the tree represents a string of n symbols comprising a key. Each node is capable of having m possible entries corresponding to m possible symbol values. Each entry comprises a pointer to a son node and an existence map indicating which entries exist in the son node. In the preferred embodiment, the existence map is a bit mask that indicates, based on bit positions enabled and disabled in the bit mask, which entries exist in the son node pointed to by the pointer. By providing an existence map along with the pointer to a son node, m memory locations for m entries are allocated for the son node only if all of the m possible entries are used.

Abstract: A multitasking computer system having multiple parallel and independently executing processors. Each processor has multiple pipeline stages. Each stage in the pipeline can be simultaneously executing a process. More processes than the sum of pipeline stages for all processors exist at any given time, which allows processes to migrate between processors and allows the processes queued at any one processor to increase, i.e., back up, momentarily without causing other processors to sit idle. Related to the ability to support at least as many processes as there are the sum of pipeline stages in all of the processors is the ability of the preferred embodiment of the present invention to migrate processes between processors. When a processor completes execution of an instruction for a particular process, the program counter for the process is incremented to point to the next instruction in the process. The process is then requeued by a scheduler.

Abstract: A method for searching for keys of arbitrary width in a table in a memory of a computer system by repeatedly executing lookup instructions on a lookup processor. The lookup processor executes a lookup instruction to find a key in a table. The execution of the lookup instruction results in a key being found, or a key not being found. If the key is not found, the process is requeued by a scheduler with the program counter register for the process pointing to the instruction immediately following the lookup instruction, i.e., the next instruction. In the event the key is found in the table, the entry in the table associated with the key contains the memory address of the next instruction to be executed. This memory address is loaded into the program counter register associated with the process in which the lookup instruction was executed. The scheduler requeues the process, later dequeues it, and the instruction pointed to by the program counter register is fetched by an instruction fetch unit.