Patents by Inventor Richard L. Arndt

Richard L. Arndt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11074205
    Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
  • Patent number: 10831593
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10614010
    Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The backlog counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10585744
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10572337
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10545816
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10528418
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Publication number: 20190370198
    Abstract: A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: RICHARD L. ARNDT, FLORIAN AUERNHAMMER, WAYNE M. BARRETT, ROBERT A. DREHMEL, GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE
  • Patent number: 10437755
    Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies an event target number, a number of bits to ignore, an event source number, and an event priority. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10423550
    Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
  • Publication number: 20190155683
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Applicant: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10289479
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Publication number: 20190121760
    Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: RICHARD L. ARNDT, FLORIAN AUERNHAMMER, WAYNE M. BARRETT, ROBERT A. DREHMEL, GUY L. GUTHRIE, MICHAEL S. SIEGEL, WILLIAM J. STARKE
  • Patent number: 10255194
    Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Benjamin Herrenschmidt, Eric N. Lais, Steven M. Thurber
  • Patent number: 10241923
    Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Benjamin Herrenschmidt, Eric N. Lais, Steven M. Thurber
  • Patent number: 10229075
    Abstract: A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10216568
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10169270
    Abstract: A technique for handling queued interrupts includes determining, by an interrupt presentation controller (IPC), whether a received memory mapped input/output (MMIO) store is associated with preempting a virtual processor (VP) thread. In response to determining the MIMO store is associated with preempting the VP thread, the IPC writes interrupt context information of the VP thread to a specified location in memory.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Publication number: 20180365179
    Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The backlog counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 20, 2018
    Inventors: RICHARD L. ARNDT, FLORIAN A. AUERNHAMMER
  • Publication number: 20180314589
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Application
    Filed: October 31, 2017
    Publication date: November 1, 2018
    Applicant: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner