Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: Systems, methodologies, media, and other embodiments associated with cache systems are described. One exemplary system embodiment includes an instruction cache comprising single-ported memories. The example system can further include a cache control logic configured to process cache events of different types that may be received by the instruction cache, and being configured with a multi-stage pipeline that coordinates processing of the cache events to the single-ported memories. The multi-stage pipeline can have different stages pre-assigned as read/write stages for the cache events to minimize access conflicts between the cache events.

Abstract: A first unit positions and then rotates an apple with a randomly oriented core. Rotation is stopped when any one of a series of aligned probes enters into one of the indents in the core of the apple. A second unit with axis of rotation at 90 degrees from the axis of rotation of the first unit takes and holds the positioned apple, and then rotates it. Rotation is stopped when a positioned probe enters into the indent in the core to align the core of the apple in the desired position to provide apple core alignment.

Abstract: Apparatus for mounting a movable superstructure on a fixed base is disclosed. The superstructure, a video display unit, is attached to a cylindrical segment journal which rests on a matching cylindrical segment socket. The journal rotates within the socket as the video display unit is tilted back and forth. Two helical springs are each attached to the superstructure and the base in such a way as to counteract gravitational forces and to tend to restore the superstructure to a neutral tilt angle when it is moved therefrom. The surfaces of the journal and socket have enough friction to exceed the relatively small differences between the gravitational forces tending to move the superstructure further from the neutral tilt angle and the spring forces tending to restore the superstructure thereto. As a result, the superstructure will maintain any position but can be moved (tilted) by overcoming only the relatively small frictional force. In one constructed model, a video display unit superstructure weighing 27.

Abstract: A belt drive clutch having a hexagonal sleeve splined on a power output shaft and carrying an outer sheave disc. A drive belt supporting annulus is freely rotatable on the sleeve and located between the outer sheave disc and an inner sheave disc. The inner sheave disc has a stud shaft extending inwardly and having a hexagonal bore matching the hexagonal external conformation on the sleeve. Ball bearings are assembled on the stud shaft and a clutch control ring is assembled on a peripheral race of the ball bearing. A camming arrangement shifts the clutch control ring axially to engage or disengage the belt by optionally constricting or expanding the space between the outer and inner sheave discs.

Abstract: A complex RF weighter provides an RF output signal controlled in amplitude and phase with respect to an input signal. The input signal is applied to a quadrature hybrid that is terminated with two PIN diodes, one of which is one-eighth wavelength farther from the hybrid than the other. Independent control of the bias on the PIN diodes provides control of the relative amplitude and phase of the output signal.

Abstract: Quarter inch plate steel forms the bottom, front and rear walls of a U-shaped open sided saddle for mounting therewithin a 9 H.P. four cycle gasoline engine, the bottom of said saddle being clamped along its front edge to a 30 inch fixed axle on opposite ends of which are freely rotatable 14 inch diameter ballon tired wheels. Rectangularly rigidly connected to upper ends of said spaced rear and front engine saddle walls and continuing 46 inches forwardly therefrom is an inverted 4 inch square U-cross section sheet metal channel providing a drill supporting tongue for the tool while also housing a main shaft, the rear end of which journals in a self-aligning bearing fixed rockably on said rear engine saddle wall. Behind said wall said main shaft has a driven pulley fixed thereon which is belt driven from an engine shaft drive pulley when a manually controlled idler roller clutch means tightens the connecting belt.

Abstract: A cutter assembly wherein material to be cut passes underneath a cutter bar, a track extending under the cutter bar holds a moveable carriage, a rotatable cutter wheel mounts to the carriage, with a side against the face of the cutter bar, a releasable gripper bar holds the material against the underside of the cutter bar during the cutting cycle, cords attached to the slideable carriage are used to pull the carriage along the track, and means are provided to attach the assembly to a support. A cutter as above mounted in a frame, and having an electric drive motor with controls for moving the carriage, and a cutter as above which is moved by a handle attached to the carriage are also disclosed.