Abstract: A lock operator for operating locking rods in a roll-up door locking mechanism in a truck or trailer comprises a pneumatic drive cylinder for each locking rod that reciprocates the locking rod between its locked and unlocked positions. A button-operated actuator valve located at the front of the truck trailer connects the truck pressurized air system to all of the drive cylinders to lock the locking rods at all four comers of the trailer simultaneously. A spring or double acting cylinder return mechanism unlocks the locking mechanism when the air pressure is relieved. The pneumatic operators are mounted on mounting plates between the inside and outside skins of the trailer and are accessible through removable inspection plates on the inside of the trailer. Each drive cylinder is linked to a locking bar by a vertically reciprocable yoke mechanism.

Abstract: An improved fluorescent lamp is disclosed. The lamp of the present invention includes an envelope containing an ionizable medium including mercury and having electrodes located within the envelope; an aluminum oxide reflector layer on the inner surface of the envelope, and a phosphor layer disposed on the reflector layer. The aluminum oxide reflector layer comprises particles of high purity aluminum oxide having an average particle size greater than 0.5 micrometer and less than or equal to about 1 micrometer and having a surface area of about 4 to 6 meter.sup.2 /gram. The aluminum oxide reflector layer preferably includes at least 95 weight percent alpha-alumina. Preferred coating weights for the reflector layer are from about 8.8 to about 11.1 milligram/square centimeter.

Abstract: A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

Abstract: A high speed, low component count, exclusive NOR gate in one embodiment comprising two input transistors whose emitters are connected to the bases of a pair of cross-coupled transistors with the collectors of the latter being connected in common and forming the output of the gate so that the current flow through the emitter cross-coupled transistors is controlled by the base voltages of the two input transistors such that an exclusive NOR gate arrangement is provided. In another embodiment, a pair of Schottky diodes are disposed between the emitters of the input transistors and the cross-coupled emitter transistors to bias the bases of the latter and to change the input signal levels required.

Abstract: An EFL D-type latch having both true and complement output with a data input transistor and a bistable storage cell comprising first and second transistors, at least one of which is multi-emitter, connected such that the true output is connected to the collector of the first transistor of the storage cell and the complement output is connected to the collector of the data input transistor and the second transistor of the storage cell to take advantage of the phase inversion of the latter transistors depending upon which one of these transistors has current flowing therethrough. Also described is an EFL type complement output circuit connected as a D-type master-slave flip-flop, an RS latch, and a JK master-slave flip-flop using an RS master latch and a D-type slave latch. Also disclosed is a toggle flip-flop implemented with a D-type flip-flop to complete an EFL type logic family.