Abstract: The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.

Abstract: An improved signal synchronizing circuit for prohibiting signals traveling from a first clock domain operating with a first clock to a second clock domain operating with a second clock when the first clock is not active. The synchronizing circuit comprising at least one signal receiving module for receiving at least one selected signal in the first clock domain, a detection circuit producing a detection signal indicating that the first clock is active, and at least one output selection module for passing the selected signal from the first clock domain to the second clock domain when the first clock is active.

Abstract: A method and system for terminating unnecessary processing of at least one multi-clock conditional instruction in a processor. The conditional instruction is processed through a processing pipeline including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. It is determined whether the conditional instruction is executable in the execute stage based on whether one or more conditions are fulfilled. If the conditional instruction is being processed in both the decode and execute stages, the conditional instruction is terminated in the decode stage if the conditional instruction is not to be executed in the execute stage. The conditional instruction may also be terminated in the intermediate processing stages. Early termination of such a conditional instruction saves processing resources and reduces power consumption of the processor.

Abstract: A method and system is disclosed for predicting whether a conditional instruction is to be executed in a processor. The processor processes instructions through processing stages including at least a decode stage, an execute stage, and one or more intermediate processing stages therebetween. First, a current condition status of the processor is detected, wherein the condition status shows whether one or more conditions for executing the conditional instruction have been satisfied. After detecting whether one or more associated instructions as being processed during the intermediate processing stages have impacted or will impact the conditions to be satisfied, it is determined whether the conditional instruction should be terminated at the decode stage based on the detected current condition status and the detected impact on the conditions due to the processing of the associated instructions.

Abstract: An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

Abstract: An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.

Abstract: A circuit for voltage translation includes protection against gate oxide breakdown when translating a lower voltage signal into a higher voltage signal. An input signal inverter circuit inverts the lower voltage signal into an intermediate signal having an increased minimum value. By raising the maximum value of the intermediate signal to the voltage level of the higher voltage signal, an output signal inverter circuit produces a driving signal to drive an output stage. However, because the increased minimum value of the signal is maintained, the gate oxide breakdown voltage is not exceeded in the circuit. The circuit also includes a blocking transistor between the input signal inverter and the output signal inverter to prevent the larger driving signal from overloading the input inverter circuit.

Abstract: An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

Abstract: A clock system includes internal monitor circuitry such that the clock system is testable in a secure environment. In particular, the clock system includes a plurality of separately enableable clock generator circuit modules. Each of the clock generator circuit modules generates a separate clock signal when enabled. Combining circuitry receives the separate clock signals from those clock generator circuit modules which are enabled and derives a derived clock signal therefrom. Monitor circuitry receives the derived clock signal, detects whether there are transitions in the derived clock signal, and provides a monitor indication of a result of the detection. Thus, the clock system can be tested without providing the separate clock signals outside the clock system. Preferably, the clock system also includes a programmable clock control register that holds clock control data, the clock control data determining which of the clock generator circuit modules are enabled.

Abstract: A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.

Abstract: The present invention provides input and output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds the internal power supply voltage or when the buffer is powered down. An isolation transistor is connected in series with a pull-up transistor between the internal power supply and the output terminal which is connected to the bus. A circuit that controls the pull-up transistor in response to an enable signal and a data input signal, controls also the isolation transistor so that when the driver is enabled and the pull-up transistor is on, the isolation transistor is also on allowing the pull-up transistor to drive the output terminal. A transistor between the circuit and the isolation transistor gate isolates the gate from the circuit when the driver is disabled. Thus, when the driver is disabled, the circuit does not control the isolation transistor.

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Abstract: The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present.

Abstract: A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.

Abstract: The present invention provides in some embodiments output buffers and input/output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds in magnitude the internal power supply voltage or when the module is powered down. This functionality is achieved as follows in some embodiments. A PMOS isolation transistor is connected in series with a pull-up transistor between the internal power supply and the buffer output terminal connected to the bus. The gate of the isolation transistor is connected through a PMOS transistor P to the output terminal and through an NMOS transistor N to ground. The gates of transistors P and N are connected to each other. When the driver is enabled and the pull-up transistor is on, the gates of transistors P and N are high. Transistor P is therefore off. Transistor N is on grounding the gate of the isolation transistor. The isolation transistor turns on allowing the pull-up transistor to drive the output terminal.

Abstract: A self-contained downhole apparatus for being lowered into an oil or gas well to internally record samples of at least one environmental condition comprises three body sections linearly and releasably interconnected. One of the body sections is a selected one of a plurality of transducer housing sections. The selected transducer housing section is mechanically and electrically connected to a second body section containing microcomputer-operated signal processing circuitry. The third body section contains a power supply.

Abstract: A self-contained memory gauge includes either semiconductor or magnetic core memory for retaining downhole information related to sampled parameters, such as borehole temperature and pressure. A microprocessor-based computer manages the power utilization by independently and selectably energizing and de-energizing different sections of the gauge. The magnetic core memory is tested for operability, and the addressing of the magnetic core memory is adjusted in accordance with any inoperable memory locations. Samples of the monitored environmental conditions can be taken at variable rates dependent upon software monitoring of the condition, the remaining battery life and the remaining memory capacity and in response to hardware monitored pressure changes. Each sample can be taken to a selectable resolution. A watchdog circuit monitors the microprocessor to insure that it is operating within a preselected time limit.

Abstract: In an oil well instrumentation system, the downhole sensor system is controlled by a computer which is powered-on only during sampling movement. An independent circuit, continuously powered, detects significant sensor rate-of-change values whereby the computer-sampling equipment is powered-on. A self-contained memory gauge includes either semiconductor or magnetic core memory for retaining downhole information related to sampled parameters, such as borehole temperature and pressure. A microprocessor-based computer manages the power utilization by independently and selectably energizing and deenergizing different sections of the gauge. The magnetic core memory is tested for operability, and the addressing of the magnetic core memory is adjusted in accordance with any inoperable memory locations.

Abstract: A method of discriminating between linear and nonlinear regions of measured data is based upon two hypotheses, one of which is a hypothesis that a response is merely a result of inherent randomness and the other of which is a hypothesis that the response is a result of a true nonlinear change greater than a value M. It is also based upon a relative cost between accepting the latter hypothesis when the former is true versus accepting the former hypothesis when the latter is true. A resulting probabilistic criterion (M/2)+(.sigma..sup.2 /M) [1n(P.sub.H0 /P.sub.H1)C] is graphically implemented for deriving offset values which can be used in a specific embodiment to construct tabular values defining linear/nonlinear regions from a presumed hypothetical straight line response.

Abstract: The power-conversing apparatus includes a plurality of independently energizable electrical circuits used in receiving electrical signals from a transducer which senses an environmental condition, in processing the electrical signals, and in storing information related to the detected environmental condition. The apparatus further includes a power control circuit for continuously providing electrical power to at least one of the electrical circuits and for independently switchably providing electrical power to selectable ones of at least two others of the separately energizable circuits.