Abstract: A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.

Abstract: A digital integrator (22) reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder (51). In the z-domain, he transfer function of a two-stage integrator can be expressed as H(z)=(1/(1-z.sup.-1)).sup.2. Expanded, the transfer function is expressed as H(z)=(1/(1 -2z.sup.-1 +z.sup.-2)). The inverse z-transform yields the expression y[n]=x[n]+2y[n-1]-y[n-2], which can be implemented with a single adder (51) and two delay portions (52, 55 and 53, 54). In one embodiment, a three-stage integrator (22) can further be implemented within a single adder circuit (91) by time-multiplexing an addition required for the two-stage integration with an addition required for a one-stage integration inside the adder circuit (91).