Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

Abstract: A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Abstract: Techniques are provided for phase-locked loop (PLL) configuration, based on a calibrated lookup table (LUT). A methodology implementing the techniques according to an embodiment includes selecting one of a number of voltage controlled oscillators (VCOs) of the PLL, and selecting a tuning parameter to control the VCO. The method further includes testing the PLL, using multiple loop divider values, to determine a minimum and maximum value that define the lower and upper bounds of a range of loop divider values for which the PLL achieves a locked state while using the selected VCO and tuning parameter. The method further includes storing PLL configuration parameters to an entry in the configuration LUT, the PLL configuration parameters to include an identification of the selected VCO, the selected tuning parameter, the minimum loop divider value, and the maximum loop divider value. The method iterates using additional combinations of selected VCOs and tuning parameters.