Abstract: In one or more embodiments, an information handling system (IHS) manufacturer is configured to: manufacture multiple motherboards configured to be installed in multiple IHS product lines; respectively install multiple non-volatile memory media on the multiple motherboards; store first product line firmware, associated with a first product line of the IHS manufacturer, via the multiple non-volatile memory media; provide a first portion of the multiple motherboards to a first division; and provide a second portion of the multiple motherboards to a second division; the first division is configured to: permanently store a first IHS identity type on the first portion of the multiple motherboards; and the second division is configured to: permanently store a second IHS identity type on the second portion of the multiple motherboards; and store second product line firmware via non-volatile memory media of the second portion of the multiple motherboards.

Abstract: An information handling system sets up at power-on self-test, a system management interrupt based on a trap on an input/output port used for a real-time clock and detects at runtime, an operation on the input/output port. In response to detecting the operation on the input/output port, generates the system management interrupt based on the trap on the input/output port. In addition, the information handling system handles the system management interrupt by emulating the real-time clock according to the operation on the input/output port that includes determining a register that is mapped to an index associated with the operation and accessing the register and executing a function associated with the register.

Abstract: In one or more embodiments, an information handling system (IHS) manufacturer is configured to: manufacture multiple motherboards configured to be installed in multiple IHS product lines; respectively install multiple non-volatile memory media on the multiple motherboards; store first product line firmware, associated with a first product line of the IHS manufacturer, via the multiple non-volatile memory media; provide a first portion of the multiple motherboards to a first division; and provide a second portion of the multiple motherboards to a second division; the first division is configured to: permanently store a first IHS identity type on the first portion of the multiple motherboards; and the second division is configured to: permanently store a second IHS identity type on the second portion of the multiple motherboards; and store second product line firmware via non-volatile memory media of the second portion of the multiple motherboards.

Abstract: An information handling system includes a processor and memory devices that each include a voltage regulator configured to be enabled by a command from the processor. The processor boots the information handling system, including providing the command to the memory devices, and detects that one of the memory devices failed to boot. The processor determines that it is unknown whether the failing memory device is the first memory device or the second memory device. In response, the processor determines which one of the memory devices failed to boot, by rebooting the information handling system, providing a command to a selected one of the memory devices, and determining whether or not the selected one of the memory devices failed to boot.

Abstract: Systems and methods are provided that may be implemented to use memory as a shared interface between a management controller (e.g., such as embedded baseboard management controller “BMC”, embedded service processor, non-embedded management controller, etc.) and a network controller of an information handling system (e.g., such as a server) in order to achieve a relatively high speed data path between a network and the management controller, and without requiring the use and/or presence of a high speed physical connection to and/or from a sideband interface of the network controller.

Abstract: An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

Abstract: Systems and methods are provided that may be implemented to use memory as a shared interface between a management controller (e.g., such as embedded baseboard management controller “BMC”, embedded service processor, non-embedded management controller, etc.) and a network controller of an information handling system (e.g., such as a server) in order to achieve a relatively high speed data path between a network and the management controller, and without requiring the use and/or presence of a high speed physical connection to and/or from a sideband interface of the network controller.

Abstract: An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

Abstract: A system and method of delaying power-up of an information handling system is disclosed. According to an aspect, a method of powering an information handling system can include detecting a delay power-up setting within a basic input output system (BIOS) of a particular information handling system using a management controller. The management controller can be configured to delay power-up of the particular information handling system. The method can further include enabling a power-up of the particular information handling system in response to the delay power-up setting using the management controller.

Abstract: A system and method of delaying power-up of an information handling system is disclosed. According to an aspect, a method of powering an information handling system can include detecting a delay power-up setting within a basic input output system (BIOS) of a particular information handling system using a management controller. The management controller can be configured to delay power-up of the particular information handling system. The method can further include enabling a power-up of the particular information handling system in response to the delay power-up setting using the management controller.

Abstract: A system and method of delaying power-up of an information handling system is disclosed. According to an aspect, a method of powering an information handling system can include detecting a delay power-up setting within a basic input output system (BIOS) of a particular information handling system using a management controller. The management controller can be configured to delay power-up of the particular information handling system. The method can further include enabling a power-up of the particular information handling system in response to the delay power-up setting using the management controller.

Abstract: A system and method of delaying power-up of an information handling system is disclosed. According to an aspect, a method of powering an information handling system can include detecting a delay power-up setting within a basic input output system (BIOS) of a particular information handling system using a management controller. The management controller can be configured to delay power-up of the particular information handling system. The method can further include enabling a power-up of the particular information handling system in response to the delay power-up setting using the management controller.