Patents by Inventor Richard L. Hudson
Richard L. Hudson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220027210Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate a second task from the workload to a second work queue, second computation circuitry to process the second task in the second work queue. The apparatus further includes first work stealer logic to steal the second task from the second work queue using an atomic operation to access the second work queue.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
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Patent number: 11138048Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.Type: GrantFiled: December 27, 2016Date of Patent: October 5, 2021Assignee: Intel CorporationInventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
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Publication number: 20170109213Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.Type: ApplicationFiled: December 27, 2016Publication date: April 20, 2017Applicant: Intel CorporationInventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
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Patent number: 9507714Abstract: Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.Type: GrantFiled: March 27, 2014Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Stephan A. Herhut, Richard L. Hudson, Tatiana Shpeisman
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Publication number: 20160154677Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.Type: ApplicationFiled: March 15, 2013Publication date: June 2, 2016Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
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Publication number: 20150279464Abstract: Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Inventors: Stephan A. Herhut, Richard L. Hudson, Tatiana Shpeisman
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Patent number: 8954986Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.Type: GrantFiled: December 17, 2010Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
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Patent number: 8306649Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operations such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the disclosure.Type: GrantFiled: June 21, 2011Date of Patent: November 6, 2012Assignee: APM Terminals North America, Inc.Inventors: Guy Alan Buzzoni, Richard L. Hudson, Edward McCarthy, Peter Giugliano
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Publication number: 20120159495Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Inventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
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Publication number: 20110251716Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operation's such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the disclosure.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Inventors: Guy Alan BUZZONI, Richard L. Hudson, Edward McCarthy, Peter Giugliano
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Patent number: 7987017Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operations such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the invention.Type: GrantFiled: February 23, 2006Date of Patent: July 26, 2011Assignee: APM Terminals North America, Inc.Inventors: Guy Allen Buzzoni, Richard L. Hudson, Edward McCarthy, Peter Giugliano
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Patent number: 7913236Abstract: A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.Type: GrantFiled: September 29, 2006Date of Patent: March 22, 2011Assignee: Intel CorporationInventors: Ali-Reza Adl-tabatabai, Vijay Menon, Richard L. Hudson, Bratin Saha, Tatiana Shpeisman
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Patent number: 7809903Abstract: Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.Type: GrantFiled: December 15, 2005Date of Patent: October 5, 2010Assignee: Intel CorporationInventors: Ali-Reza Adl-tabatabai, Bratin Saha, Richard L. Hudson, Haitham Akkary, Ravi Rajwar
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Patent number: 7577947Abstract: Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.Type: GrantFiled: December 19, 2003Date of Patent: August 18, 2009Assignee: Intel CorporationInventors: Sreenivas Subramoney, Mauricio J. Serrano, Richard L. Hudson, Ali-Reza Adl-Tabatabai
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Patent number: 7542977Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.Type: GrantFiled: June 29, 2006Date of Patent: June 2, 2009Assignee: Intel CorporationInventors: Richard L. Hudson, Ali-Reza Adl-tabatabai, Bratin Saha
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Patent number: 7478210Abstract: Memory reclamation with optimistic concurrency is described. In one example an allocated memory object is tentatively freed in a software transactional memory, the object having pointers into it from at least one transaction. A time when all transactions that are outstanding at the time an object is tentatively freed have ended is detected, and the object is actually freed based on the detection.Type: GrantFiled: June 9, 2006Date of Patent: January 13, 2009Assignee: Intel CorporationInventors: Bratin Saha, Richard L. Hudson, Ali-Reza Adl-tabatabai
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Patent number: 7389385Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.Type: GrantFiled: December 19, 2003Date of Patent: June 17, 2008Assignee: Intel CorporationInventors: Mauricio J. Serrano, Sreenivas Subramoney, Richard L. Hudson, Ali-Reza Adl-Tabatabai
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Publication number: 20080098374Abstract: A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 29, 2006Publication date: April 24, 2008Inventors: Ali-Reza Adl-tabatabai, Vijay Menon, Richard L. Hudson, Bratin Saha, Tatiana Shpeisman
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Publication number: 20080021934Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.Type: ApplicationFiled: June 29, 2006Publication date: January 24, 2008Inventors: Richard L. Hudson, Ali-Reza Adl-tabatabai, Bratin Saha
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Publication number: 20070288708Abstract: Memory reclamation with optimistic concurrency is described. In one example an allocated memory object is tentatively freed in a software transactional memory, the object having pointers into it from at least one transaction. A time when all transactions that are outstanding at the time an object is tentatively freed have ended is detected, and the object is actually freed based on the detection.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: Bratin Saha, Richard L. Hudson, Ali-Reza Adl-tabatabai