Patents by Inventor Richard L. Hudson

Richard L. Hudson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220027210
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate a second task from the workload to a second work queue, second computation circuitry to process the second task in the second work queue. The apparatus further includes first work stealer logic to steal the second task from the second work queue using an atomic operation to access the second work queue.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
  • Patent number: 11138048
    Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
  • Publication number: 20170109213
    Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
  • Patent number: 9507714
    Abstract: Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Stephan A. Herhut, Richard L. Hudson, Tatiana Shpeisman
  • Publication number: 20160154677
    Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 2, 2016
    Inventors: Rajkishore Barik, Stephan A. Herhut, Jaswanth Sreeram, Tatiana Shpeisman, Richard L. Hudson
  • Publication number: 20150279464
    Abstract: Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Stephan A. Herhut, Richard L. Hudson, Tatiana Shpeisman
  • Patent number: 8954986
    Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
  • Patent number: 8306649
    Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operations such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the disclosure.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 6, 2012
    Assignee: APM Terminals North America, Inc.
    Inventors: Guy Alan Buzzoni, Richard L. Hudson, Edward McCarthy, Peter Giugliano
  • Publication number: 20120159495
    Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
  • Publication number: 20110251716
    Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operation's such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the disclosure.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Inventors: Guy Alan BUZZONI, Richard L. Hudson, Edward McCarthy, Peter Giugliano
  • Patent number: 7987017
    Abstract: A system and process for improving container flow within a port facility, including improved equipment and software for controlling operation and flow of the equipment in the part facility. The system may include a port facility geographically arranged to separate land operations and water operations. Land operations such as over-the-road missions and rail missions may use landside access areas positioned at one end of a yard including rows of container stacks. Water missions such as loading/discharging a vessel may use waterside access areas positioned at the opposite end of the yard. Automated cranes linked with a terminal operating system may pick/drop/shuffle containers and/or refrigerated containers (“reefers”) within the container stacks. Shuttle trucks may be used to pick/drop containers at quayside access points and the waterside access areas. The shuttle trucks may utilize shared wheelpaths. Software systems may be used to implement various principles of the invention.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: July 26, 2011
    Assignee: APM Terminals North America, Inc.
    Inventors: Guy Allen Buzzoni, Richard L. Hudson, Edward McCarthy, Peter Giugliano
  • Patent number: 7913236
    Abstract: A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-tabatabai, Vijay Menon, Richard L. Hudson, Bratin Saha, Tatiana Shpeisman
  • Patent number: 7809903
    Abstract: Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: October 5, 2010
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-tabatabai, Bratin Saha, Richard L. Hudson, Haitham Akkary, Ravi Rajwar
  • Patent number: 7577947
    Abstract: Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Sreenivas Subramoney, Mauricio J. Serrano, Richard L. Hudson, Ali-Reza Adl-Tabatabai
  • Patent number: 7542977
    Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventors: Richard L. Hudson, Ali-Reza Adl-tabatabai, Bratin Saha
  • Patent number: 7478210
    Abstract: Memory reclamation with optimistic concurrency is described. In one example an allocated memory object is tentatively freed in a software transactional memory, the object having pointers into it from at least one transaction. A time when all transactions that are outstanding at the time an object is tentatively freed have ended is detected, and the object is actually freed based on the detection.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: January 13, 2009
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Richard L. Hudson, Ali-Reza Adl-tabatabai
  • Patent number: 7389385
    Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Mauricio J. Serrano, Sreenivas Subramoney, Richard L. Hudson, Ali-Reza Adl-Tabatabai
  • Publication number: 20080098374
    Abstract: A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 24, 2008
    Inventors: Ali-Reza Adl-tabatabai, Vijay Menon, Richard L. Hudson, Bratin Saha, Tatiana Shpeisman
  • Publication number: 20080021934
    Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 24, 2008
    Inventors: Richard L. Hudson, Ali-Reza Adl-tabatabai, Bratin Saha
  • Publication number: 20070288708
    Abstract: Memory reclamation with optimistic concurrency is described. In one example an allocated memory object is tentatively freed in a software transactional memory, the object having pointers into it from at least one transaction. A time when all transactions that are outstanding at the time an object is tentatively freed have ended is detected, and the object is actually freed based on the detection.
    Type: Application
    Filed: June 9, 2006
    Publication date: December 13, 2007
    Inventors: Bratin Saha, Richard L. Hudson, Ali-Reza Adl-tabatabai