Abstract: An embodiment of a hinge has a first part with a pin, the pin defining a longitudinal axis, and a second part with a receptacle for the pin. The first and second parts are arranged to rotate relative to one another about the axis with the pin in the receptacle. Mutually cooperating formations on the pin and receptacle are arranged to permit separation of the first and second parts along the axis in a first position of relative rotation of the first and second parts and to obstruct separation of the first and second parts along the axis in a second position of relative rotation of the first and second parts.

Abstract: An improved avionics display unit graphically presents meteorological phenomena data to a pilot enroute utilizing conventional pilot report (PIREP) information which includes meteorological phenomena data including phenomena location data. The avionics display unit generates an icon defined by the meteorological phenomena data of the PIREP information and presents the icon on a display of the avionics display unit overlaying a map display at an icon location determined in response to the phenomena location data of the PIREP information.

Abstract: A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units comprised of semiconductor dynamic random access memory chips, logic is provided within the system to provide for the single stepping of the central processing unit clock thereby allowing for the execution of one CPU cycle. The system logic is organized such that the memory refresh command signals, which are normally generated by the CPU, are generated by the single step logic thereby maintaining the contents of the main memory modules. The logic of the overall data processing system is organized such that most transfers of information between the main memory, the CPU and I/O controllers, to which peripheral devices are connected, may take place in the single step mode of operation without the loss of information.

Abstract: In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.