Patents by Inventor Richard L. Kleinhenz

Richard L. Kleinhenz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8634949
    Abstract: A solution for managing a manufacturing environment using operating data for each of a plurality of tools in the manufacturing environment. The operating data can include actual resource consumption data and/or actual exhaust generation data for a tool while the tool implements at least a portion of a recipe to manufacture one of a plurality of types of products manufactured in the manufacturing environment. Operation of the manufacturing environment can be configured to optimize one or more aspects of resource consumption and/or exhaust generation during the manufacture of desired quantities of the plurality of types of products within a desired time frame using the operating data.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian C. Barker, Edward P. Higgins, Richard L. Kleinhenz, Gary R. Moore, Mark L. Reath, Justin W. Wong, Horst Zisgen
  • Publication number: 20110288668
    Abstract: A solution for managing a manufacturing environment using operating data for each of a plurality of tools in the manufacturing environment. The operating data can include actual resource consumption data and/or actual exhaust generation data for a tool while the tool implements at least a portion of a recipe to manufacture one of a plurality of types of products manufactured in the manufacturing environment. Operation of the manufacturing environment can be configured to optimize one or more aspects of resource consumption and/or exhaust generation during the manufacture of desired quantities of the plurality of types of products within a desired time frame using the operating data.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian C. Barker, Edward P. Higgins, Richard L. Kleinhenz, Gary R. Moore, Mark L. Reath, Justin W. Wong, Horst Zisgen
  • Publication number: 20020187619
    Abstract: A method for gettering metallic impurities located in a semiconductor substrate. In an exemplary embodiment of the invention, the method includes forming an insulating layer upon a donor wafer. A cleaving layer is ionically implanted, through the insulating layer, into the donor wafer. The cleaving layer is formed at a first depth with respect to the insulating layer. A gettering layer is also ionically implanted, through the insulating layer, into the donor wafer. The gettering layer is formed at a second depth with respect to said insulating layer, with second depth being less than the first depth. The donor wafer is then bonded, at the insulating layer, to a substrate wafer. The donor wafer is then fractured along the cleaving layer, and a section of the donor wafer is removed along the cleaving layer. Thereby, an active semiconductor device area is formed atop the gettering layer.
    Type: Application
    Filed: May 4, 2001
    Publication date: December 12, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Kleinhenz, Daniel Moy, Robert E. Bendernagel, Harold J. Hovel
  • Patent number: 6190955
    Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: February 20, 2001
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp., Kabushiki Kaisha Toshiba
    Inventors: Matthias Ilg, Richard L. Kleinhenz, Soichi Nadahara, Ronald W. Nunes, Klaus Penner, Klaus Roithner, Radhika Srinivasan, Shigeki Sugimoto
  • Patent number: 6140175
    Abstract: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Kleinhenz, Carl J. Radens
  • Patent number: 6107135
    Abstract: A method of forming a buried plate electrode for a trench capacitor of a semiconductor memory device is provided. Trenches are formed in a semiconductor substrate and a dopant source film is formed on the sidewalls and bottom walls of the trenches. A resist is formed on the dopant source film which fills in the trenches. The resist is recessed to remain in the trenches at a level which is below the surface of the semiconductor substrate. Impurities are implanted into the semiconductor substrate using the recessed resist as a block mask. The dopant source film is etched using the recessed resist as an etching mask and the recessed resist is then removed. The implanted impurities and dopants from the dopant source film are diffused into the semiconductor substrate to form a buried plate electrode.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: August 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Richard L. Kleinhenz, Gary B. Bronner, Junichiro Iba
  • Patent number: 6074951
    Abstract: Hydrogen fluoride undercut of oxide layers may be reduced by using a low pressure mixture of gaseous hydrogen fluoride and gaseous ammonia mixture. Organic photoresists can be used as a masking material when using the gaseous hydrogen fluoride/ammonia mixture without resulting in an enhanced reaction rate. In addition, because of the reaction conditions, the dimensions in the oxide layer being etched can be specifically sized smaller than openings made in the overcoating masking material.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Kleinhenz, Wesley C. Natzle, Chienfan Yu
  • Patent number: 6071815
    Abstract: A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits includes the steps of forming an insulator layer on sidewalls of a trench in a substrate with a horizontal top surface above the sidewalls, recessing a masking material such as an organic photoresist in the trench below the top surface of the substrate such that a portion of the insulator layer on the sidewalls of the substrate is exposed, and etching the insulator layer with a gaseous hydrogen flouride-ammonia mixture. The masking material and the substrate are composed of a different material than the insulator layer.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: June 6, 2000
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Kleinhenz, Wesley C. Natzle, Chienfan Yu
  • Patent number: 5970009
    Abstract: Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: October 19, 1999
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Heinz Hoenigschmid, Richard L. Kleinhenz, Jack A. Mandelman
  • Patent number: 5876879
    Abstract: Hydrogen fluoride undercut of oxide layers may be reduced by using a low pressure mixture of gaseous hydrogen fluoride and gaseous ammonia mixture. Organic photoresists can be used as a masking material when using the gaseous hydrogen fluoride/ammonia mixture without resulting in an enhanced reaction rate. In addition, because of the reaction conditions, the dimensions in the oxide layer being etched can be specifically sized smaller than openings made in the overcoating masking material.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: March 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Kleinhenz, Wesley C. Natzle, Chienfan Yu
  • Patent number: 5838055
    Abstract: Hydrogen fluoride undercut of oxide layers may be reduced by using a low pressure mixture of gaseous hydrogen fluoride and gaseous ammonia mixture. Organic photoresists can be used as a masking material when using the gaseous hydrogen fluoride/ammonia mixture without resulting in an enhanced reaction rate. In addition, because of the reaction conditions, the dimensions in the oxide layer being etched can be specifically sized smaller than openings made in the overcoating masking material.
    Type: Grant
    Filed: May 29, 1997
    Date of Patent: November 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Kleinhenz, Wesley C. Natzle, Chienfan Yu