Abstract: An IC having closely packed rows of cells enables both regular structures (register stacks and memories) and random logic structures to be efficiently fabricated from it. Circuits having more parallel-to-the-length-of-the-rows interconnecting wiring than regular structures have wiring corridors over inactive rows of cells whose cells are not connected into the circuit. A grid power bus structure smooths power flow with a minimum of active device loss by hyphenating "large" cells across the cell-row-crossing conductors.

Abstract: High gate count integrated circuits (ICs) are designed in a heirarchical manner. In a first pass through a computer design system basic cells are composed to form one-level-up building block cells. In a second pass through the same computer design system the one-level-up building block cells are used as "basic" cells and composed to form a two-level-up structure which may be a building block cell or a chip.

Abstract: A first IGFET functioning as a pull-up or pull-down transistor is formed in parallel with one of a pair of gated diodes. The first IGFET-diode combination is connected to the gate electrode of a second IGFET to which is connected an external (off chip) signal source. In one mode of operation, the first IGFET is turned-on in response to a control signal and operates as a current path to prevent the gate of the second IGFET from floating in the event of an open circuit. In a second mode of operation, the second IGFET is turned-off in response to a control signal. The diode portion of the combination operates to protect the gate electrode of the second IGFET from any over voltage.

Abstract: A folded-cascode amplifier arrangement includes first and second transistors of complementary conductivity type and a constant current generator for supplying quiescent current thereto. Signal current flowing in the first transistor is coupled to the second transistor through current steering at the interconnection between their main conduction paths. The load means for the second transistor includes a cascode-connected third transistor for supplying load current thereto, which third transistor substantially increases the resistance of the load for correspondingly increasing the voltage gain of the amplifier arrangement. The amplifier voltage gain transfer function exhibits a frequency response dominated by a single pole.

Abstract: A folded-cascode amplifier arrangement includes first and second transistors of complementary conductivity type and a constant current generator for supplying quiescent current thereto. Signal current flowing in the first transistor is coupled to the second transistor through current steering at the interconnection between their main conduction paths. Signal current flowing in the first transistor is further coupled to the input circuit of a current mirror amplifier (CMA), the output current of which is proportional to the signal current and is coupled to the main conduction path of the second transistor. The output current of the CMA is poled for reinforcing the current flow of the second transistor so that the output current available from the folded-cascode configuration is substantially greater than the signal current in the first transistor. The amplifier voltage-gain transfer function exhibits a frequency response dominated by a single pole.