Patents by Inventor Richard L. Schober

Richard L. Schober has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040225734
    Abstract: A method and system of communicating data between a plurality of interconnect devices are described. The method includes allocating a sequence number associated with each grant authorizing a source interconnect device to communicate the data to a destination interconnect device. The sequence number of a queued grant is then with a reference sequence number and, in response to the comparison, the data is communicated. In one embodiment, the sequence number is a grant sequence number that defines a sequence in which each grant is to be executed in response to a comparison with a reference transmit sequence number.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 11, 2004
    Inventors: Richard L. Schober, Rick Reeve, Prasad Vajjhala
  • Patent number: 6636993
    Abstract: A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: October 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Yoichi Koyanagi, Richard L. Schober, Raghu Sastry, Hirotaka Tamura
  • Publication number: 20030074609
    Abstract: A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality of deskew subsystems. The deskew controller automatically computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
    Type: Application
    Filed: November 19, 2002
    Publication date: April 17, 2003
    Inventors: Yoichi Koyanagi, Richard L. Schober, Raghu Sastry, Hirotaka Tamura
  • Patent number: 6493320
    Abstract: A method and apparatus automatically initialize and tune a link in a network system. The link couples one router to another router and may be implemented as a high speed, plesiochronous, parallel link. The apparatus includes a first link control unit coupled to a first end of the link and a second link control unit coupled to a second end of the link. The second link control unit is capable of communicating with the first link control unit to achieve automatic adjustment of the operating parameters of the link to maximize signal propagation across and minimize the power consumption of the link. The method of initializing and tuning across a high speed link in a network is also disclosed.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Richard L. Schober, Yoichi Koyanagi, Raghu Sastry, Hirotaka Tamura, Kohtaro Gotoh
  • Patent number: 6003064
    Abstract: A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: December 14, 1999
    Assignee: Fujitsu Limited
    Inventors: Thomas M. Wicki, Patrick J. Helland, Jeffrey D. Larson, Albert Mu, Raghu Sastry, Richard L. Schober, Jr.
  • Patent number: 5987629
    Abstract: A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: November 16, 1999
    Assignee: Fujitsu Limited
    Inventors: Raghu Sastry, Jeffrey D. Larson, Albert Mu, John R. Slice, Richard L. Schober, Jr., Thomas M. Wicki
  • Patent number: 5768300
    Abstract: A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: June 16, 1998
    Assignee: Fujitsu Limited
    Inventors: Raghu Sastry, Jeffrey D. Larson, Albert Mu, John R. Slice, Richard L. Schober, Jr., Thomas M. Wicki