Abstract: Circuitry for a node of an optical communication network has a mux and/or a demux. In one embodiment, the circuitry has a mux and a demux implemented on a single circuit board, where (1) the mux is configured to combine up to eight different incoming OC3/OC12-rate electrical signals into a single outgoing OC48-rate electrical signal for conversion into two copies of an outgoing OC48 optical signal and (2) the demux is configured to split a working incoming OC48-rate electrical signal (selected from two incoming OC48-rate electrical signals converted from two incoming OC48 optical signals) into up to eight different outgoing OC3/OC12-rate electrical signals. The node is configured to perform automatic signal provisioning, which may be (a) the addition of a new OC3/OC12 signal; (b) the deletion of an existing OC3/OC12 signal; (c) the rate-upgrading of an existing OC3 signal to an OC12 signal; or (d) the rate-downgrading of an existing OC12 signal to an OC3 signal.

Abstract: Circuitry for a node of an optical communication network is configured to mux (i.e., combine) one or more incoming customer signals for transmission as a single outgoing optical signal and to demux (i.e., split) an incoming optical signal into one or more outgoing customer signals, where the muxing and demuxing clocks are selected from one or more customer clocks recovered from the one or more customer signals, an input clock recovered from the incoming optical signal, and a local clock generated by a local clock generator. When configured for an add/drop configuration, the circuitry selects (1) the muxing clock from the one or more customer clocks, the input clock, and the local clock and (2) the demuxing clock from the input clock and the local clock. When configured for a drop/continue configuration, the circuitry is configured to select both the muxing and demuxing clocks from either the first input clock or the local clock.

Abstract: A microcomputer having a 4-bit instruction register uses some double operation code (opcode) instructions thereby increasing its instruction set over the sixteen instruction limit imposed by the instruction register. During a single opcode instruction operation, a 4-bit opcode word is fetched from memory (20), is loaded into the instruction register (32), and is applied to a logic circuit (601, 603 or 621, 623). The resulting output from the logic circuit (601, 603 or 621, 623) determines the state of a latching device (610 or 630). The latching device (610 or 630) is latched into a first state in response to the output of the logic circuit, and the first opcode word stored in the instruction register controls processing of a data word to be fetched from storage. During a double opcode instruction operation, a first opcode word is fetched into the instruction register. The latching device (610 or 630) is latched into a second state in response to the output of the logic circuit.