Patents by Inventor Richard L. Yeakley

Richard L. Yeakley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4982263
    Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.
    Type: Grant
    Filed: March 10, 1989
    Date of Patent: January 1, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: David B. Spratt, Eldon J. Zorinsky, Robert L. Virkus, Kenneth E. Bean, Richard L. Yeakley
  • Patent number: 4902642
    Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).
    Type: Grant
    Filed: August 24, 1988
    Date of Patent: February 20, 1990
    Assignee: Texas Instruments, Incorporated
    Inventors: Bor-Yen Mao, Richard L. Yeakley
  • Patent number: 4849370
    Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.
    Type: Grant
    Filed: December 21, 1987
    Date of Patent: July 18, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: David B. Spratt, Eldon J. Zorinsky, Robert L. Virkus, Kenneth E. Bean, Richard L. Yeakley
  • Patent number: 4810667
    Abstract: The disclosure relates to a method of forming an isolated semiconductor, preferably of the vertical bipolar variety, wherein a porous highly doped semiconductor layer is oxidized and, with a trench containing silicon oxide therein, forms a region encasing a moderately doped epitaxial layer disposed beneath a lightly doped epitaxial layer. The vertical bipolar device is formed in the moderately doped and lightly doped layers with the highly doped epitaxially deposited layer, which is now a silicon oxide layer, forming a portion of the isolation. The anodization of the highly doped layer takes place using an anodizing acid at a temperature of from about 0 to about 10 degrees C.
    Type: Grant
    Filed: April 28, 1987
    Date of Patent: March 7, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Eldon J. Zorinsky, David B. Spratt, Richard L. Yeakley