Abstract: A phase detector and signal locking system controller for use in a digital phase-locked loop (PLL) application includes a first and a second phase detector where the first phase detector result is used to control the initial pull-in and the second phase detector is used to control fine tuning once the phase differences are too small for appropriate detection by the first phase detector. A post processing and control unit operates to effectively merge the two phase detector outputs and to apply the appropriate gain factor that can be used to control a PLL system.

Abstract: A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.

Abstract: A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.

Abstract: An asynchronous timing oscillator re-synchronizer enables a clocked system which uses a high frequency clock to measure time intervals to re-synchronize to the clock after it has been temporarily disabled, using a low frequency, low accuracy, low power clock to determine the number of high frequency clock cycles that would have occurred during such intervals. Both high frequency and low frequency clocks are provided to the re-synchronizer, and the ratio between their respective frequencies is periodically determined and stored. A command sent to the re-synchronizer disables the high frequency clock for a specified number of cycles of the low frequency clock. When the disablement period has expired, the high frequency clock is re-enabled.

Abstract: A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.

Abstract: A data processing circuit (201) is shown having elements (315, 310) which operate in response to decoded instruction while receiving clocking signals. Instruction types are identified and clocking signals to at least one of the elements is enabled or disabled in dependence upon whether the element is required for the execution of the identified instruction type.

Abstract: A mobile telephone has a high frequency system clock and processing means. In a stand-by condition, when the telephone is not being used as such but is ready to receive incoming calls, polling signals are processed during a predetermined portion of a repeated periodic cycle. After completing cycle processing, the system clock is de-activated. However, it is not necessary to calculate a de-activation period. Re-activation occurs at a predetermined position within the repeated periodic cycle in anticipation of receiving the next polling signals.

Abstract: A mobile telephone has a high frequency system clock (41) and a processor (61) arranged to process polling signals received while the telephone is in its standby condition. When polling signals are not being received, it is possible for the telephone to be placed in a sleep condition, by de-activating the system clock. Re-activation occurs in response to a calibrated number of clock cycles produced by a lower frequency sleep clock (65). Upon re-activation, system clock counters (43,44), specifying sub-frame periods and frame periods are re-loaded so that they may be re-activated at the required phase. The phase of these counters is compared with signals received from base stations and modifications are made to system counts as required. The extent to which modifications are required is also used to re-calibrate the sleep clock.