Abstract: An industrial automation system for controlling the operating means of a technical process. The system includes fail-safe modules for interchanging process data with the operating means, i.e., actuating and measurement signals, stations having slots for modules, which slots are inter-connected by a backplane bus, a central processing unit at least for processing process signals from the technical process, and a field bus for transmitting data between the central processing unit and the stations. In accordance with the invention, the address relationship for the addressing of a fail-safe module by the central processing unit over the field bus for data processing purposes is permanently stored in a first memory in the respective module and is additionally permanently backed-up in the associated station.

Abstract: An industrial automation system for controlling the operating means of a technical process. The system includes fail-safe modules for interchanging process data with the operating means, i.e., actuating and measurement signals, stations having slots for modules, which slots are inter-connected by a backplane bus, a central processing unit at least for processing process signals from the technical process, and a field bus for transmitting data between the central processing unit and the stations. In accordance with the invention, the address relationship for the addressing of a fail-safe module by the central processing unit over the field bus for data processing purposes is permanently stored in a first memory in the respective module and is additionally permanently backed-up in the associated station.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract: An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: A skateboard truck is provided which comprises a base a hanger and a coupling assembly. The base has a first portion with a first hole therein and a second portion with a second hole therethrough. The hanger has an axle for mounting wheels thereon, a ring and a pin, the pin being received in the first hole. The axis of the pin coincides with the axis of the first hole and passes through the center of the ring. The coupling assembly is provided for coupling the hanger to the base, the coupling assembly passing through the ring and being received in the second hole.