Patents by Inventor Richard Louis Arndt
Richard Louis Arndt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140325163Abstract: A technique for managing shared memory includes linking address translation data structures used by first and second sharing applications. The first sharing application is managed by a first operating system (OS) and the second sharing application is managed by a second OS that hosts an associated virtual object. Virtual addresses of the first and second sharing applications are bound, based on the linking, to a changeable set of physical addresses that the second OS assigns to the associated virtual object such that the associated virtual object, which is shared by the sharing applications, is pageable by the second OS without permission of the first OS.Type: ApplicationFiled: April 25, 2013Publication date: October 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Richard Louis Arndt
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Patent number: 8782024Abstract: A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.Type: GrantFiled: February 12, 2004Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce G. Mealey, Steven Mark Thurber
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Patent number: 8719554Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.Type: GrantFiled: January 23, 2013Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier, Ronald P. Hall
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Patent number: 8719638Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.Type: GrantFiled: July 17, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier
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Patent number: 8713290Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.Type: GrantFiled: September 20, 2010Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier, Ronald P. Hall
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Patent number: 8694832Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.Type: GrantFiled: March 3, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier
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Patent number: 8356193Abstract: A method, system, and computer usable program product for scaling energy use in a virtualized data processing environment are provided in the illustrative embodiments. A set of PIOAs is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs.Type: GrantFiled: May 19, 2009Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Randal Craig Swanberg
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Patent number: 8341628Abstract: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.Type: GrantFiled: December 23, 2009Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Christopher Francois, Naresh Nayar, Karthick Rajamani, Freeman Leigh Rawson, III, Randal Craig Swanberg
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Patent number: 8327085Abstract: An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.Type: GrantFiled: May 5, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Richard Louis Arndt, David Alan Hepkin, Sergio Reyes, Kenneth Charles Vossen
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Publication number: 20120284717Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier
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Publication number: 20120226946Abstract: A processor recognizes a request from a program executing on a first hardware thread to initiate software code on a second hardware thread. In response, the second hardware thread initiates and commences executing the software code. During execution, the software code uses hardware registers of the second hardware thread to store data. Upon termination of the software code, the second hardware thread invokes a hypervisor program, which extracts data from the hardware registers and stores the extracted data in a shared memory area. In turn, a debug routine executes and retrieves the extracted data from the shared memory area.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Applicant: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier
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Patent number: 8213294Abstract: A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.Type: GrantFiled: June 27, 2006Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Thomas Schlipf, Steven Mark Thurber
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Publication number: 20120072707Abstract: A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.Type: ApplicationFiled: September 20, 2010Publication date: March 22, 2012Applicant: International Business Machines CorporationInventors: Richard Louis Arndt, Giles Roger Frazier, Ronald P. Hall
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Patent number: 8086903Abstract: A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset.Type: GrantFiled: March 31, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Patrick Allen Buckland, Harvey Gene Kiel, Renato John Recio, Jaya Srikrishnan
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Publication number: 20110276742Abstract: An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.Type: ApplicationFiled: May 5, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Richard Louis Arndt, David Alan Hepkin, Sergio Reyes, Kenneth Charles Vossen
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Patent number: 8028105Abstract: A method, computer program product, and distributed data processing system that enables host software or firmware to allocate virtual resources to one or more system images from a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, is provided. Adapter resource groups are assigned to respective system images. An adapter resource group is exclusively available to the system image to which the adapter resource group assignment was made. Assignment of adapter resource groups may be made per a relative resource assignment or an absolute resource assignment. In another embodiment, adapter resource groups are assigned to system images on a first come, first served basis.Type: GrantFiled: May 16, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giora Biran, Harvey Gene Kiel, Vadim Makhervaks, Renato John Recio, Leah Shalev, Jaya Srikrishnan
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Patent number: 8024496Abstract: An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page containing the plurality of source sub-pages in the source page, the splitter divides a plurality of high order page numbers from a plurality of low order page numbers. The selector selects the high order page number of the large page and creates an enhanced migration descriptor comprising the high order page number and a size of the large page. The selector, by the enhanced migration descriptor, combines the low order page number for a sub-page with the destination address and size of the enhanced migration descriptor to migrate the large page and each of the plurality of sub-pages.Type: GrantFiled: April 10, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventor: Richard Louis Arndt
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Patent number: 7996687Abstract: Multiple logical partitions are provided in a data processing system. A unique context is generated for each one of the logical partitions. When one of the logical partitions requires access to the hardware TPM, that partition's context is required to be stored in the hardware TPM. The hardware TPM includes a finite number of storage locations, called context slots, for storing contexts. Each context slot can store one partition's context. Each one of the partitions is associated with one of the limited number of context storage slots in the hardware TPM. At least one of the context slots is simultaneously associated with more than one of the logical partitions. Contexts are swapped into and out of the hardware TPM during runtime of the data processing system so that when ones of the partitions require access to the hardware TPM, their required contexts are currently stored in the hardware TPM.Type: GrantFiled: October 31, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Steven A. Bade, Thomas J. Dewkett, Charles W. Gainey, Jr., Nia Letise Kelley, Siegfried Sutter, Helmut H. Weber
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Patent number: 7979548Abstract: A method and system are disclosed for logically partitioning resources of a single channel adapter for use in a system area network. Each resource includes a partition identifier register within which is stored a partition identifier. A first one of the resources is assigned to a first partition by storing a first partition identifier in the partition identifier register within the first one of the resources. A second one of the resources is assigned to a second partition by storing a second partition identifier in the partition identifier register within the second one of the resources. Partitioning of the resources is enforced by permitting access to the first resource by only the first partition and permitting access to the second resource by only the second partition by checking the partition identifiers of each resource.Type: GrantFiled: September 30, 2003Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7966616Abstract: A method, system, and computer program product for sharing adapter resources among multiple operating system instances. The present invention provides a mechanism for dynamically allocating virtualized I/O adapter resources. The present invention separates the operation of adapter resource allocation from adapter resource management. Protection attributes within the adapter resource context are used to allow the adapter to enforce access control over the adapter resources. The hypervisor allocates an available adapter resource to a given partition. The adapter is notified of the allocation, and the adapter updates its internal structure to reflect the allocation. The hypervisor may revoke ownership of and reassign adapter resources to another OS instance. In this manner, the allocation described above allows for the simple reassignment of resources from one partition to another.Type: GrantFiled: March 25, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Giora Biran, Harvey Gene Kiel, Vadim Makhervaks, Renato John Recio, Leah Shalev, Jaya Srikrishnan