Abstract: An improved digital differential analyzer (DDA) circuit wherein the output pulses, representing incremental changes of an integral, are generated at a rate as determined by a remainder size number. An integrand counter responds to pulses representing an incremental change of the integrand to keep track of the correct value of the integrand. Upon the occurrance of a pulse representing an incremental change of the variable of integration the present value of the integrand is added to the number stored in a remainder register thereby generating a new remainder number. The new remainder number is compared to the programmed remainder size number and if the new remainder is equal to or greater than the remainder size number a pulse representing an incremental change of the integral is generated and the new remainder is modified by subtracting the remainder size number from the new remainder number.