Patents by Inventor Richard M. Chou

Richard M. Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Concurrent optimization of 3D-IC with asymmetrical routing layers
    Patent number: 11276677
    Abstract: Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: March 15, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Liqun Deng, Pinhong Chen, Richard M. Chou, Chin-Chih Chang, Miao Liu, Yufeng Luo
  • Method, system, and computer program product for implementing electronic designs with automatically generated power intent
    Patent number: 10204180
    Abstract: Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kai-Ti Huang, Pinhong Chen, Richard M. Chou