Patents by Inventor Richard M. Lienau
Richard M. Lienau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190384229Abstract: An electronic visible light sensor is employed to detect the presence or lack of sunlight. The simple, digital light/dark data from the sensor is fed to electronic circuits which control security and other devices dependent upon day and night status. These circuits are directed and controlled in turn by associated electronic circuits that gather data which measures the length of the solar night, that is, between dusk and dawn, and by deduction, the length of the day. Given that these time periods vary daily and in a regular fashion, the result will necessarily differ by a few minutes each and every day during the 365 day solar year. The resulting day/night time data is used to estimate, with say, a four to ten minute accuracy, taken against the Universal Coordinated Time System, to establish start/stop times, durations and cycles of security and other devices dependent upon the presence or lack of sunlight relative to UCT designated within the universally accepted twenty-four day.Type: ApplicationFiled: June 18, 2018Publication date: December 19, 2019Inventor: Richard M. Lienau
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Publication number: 20090256588Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: ApplicationFiled: November 10, 2008Publication date: October 15, 2009Applicants: PAGEANT TECHNOLOGIES, INC.Inventor: Richard M. LIENAU
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Patent number: 7463058Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: GrantFiled: August 17, 2007Date of Patent: December 9, 2008Assignees: Estancia Limited, Pageant Technologies, Inc.Inventor: Richard M. Lienau
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Publication number: 20080273368Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).Type: ApplicationFiled: July 14, 2008Publication date: November 6, 2008Inventor: Richard M. Lienau
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Patent number: 7414885Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).Type: GrantFiled: December 26, 2006Date of Patent: August 19, 2008Assignee: Optimer Pharmaceuticals, Inc.Inventor: Richard M. Lienau
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Patent number: 7285983Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: GrantFiled: October 13, 2006Date of Patent: October 23, 2007Assignees: Estancia Limited, Pageant Technologies, Inc.Inventor: Richard M. Lienau
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Patent number: 7257021Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.Type: GrantFiled: December 26, 2006Date of Patent: August 14, 2007Assignees: Pageant Technologies, Inc., Estancia LimitedInventors: Richard M. Lienau, James Craig Stephenson
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Patent number: 7187579Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.Type: GrantFiled: March 23, 2006Date of Patent: March 6, 2007Assignees: Pageant Technologies, Inc., Estancia LimitedInventors: Richard M. Lienau, James Craig Stephenson
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Patent number: 7177180Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).Type: GrantFiled: March 25, 2005Date of Patent: February 13, 2007Assignees: Pageant Technologies, Inc., Estancia LimitedInventor: Richard M. Lienau
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Patent number: 7123050Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: GrantFiled: January 18, 2005Date of Patent: October 17, 2006Inventor: Richard M. Lienau
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Patent number: 7023727Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.Type: GrantFiled: June 15, 2001Date of Patent: April 4, 2006Assignees: Pageant Technologies, Inc., Estancia LimitedInventors: Richard M. Lienau, James Craig Stephenson
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Patent number: 6873546Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).Type: GrantFiled: March 8, 2001Date of Patent: March 29, 2005Inventor: Richard M. Lienau
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Patent number: 6864711Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: GrantFiled: January 20, 2001Date of Patent: March 8, 2005Inventor: Richard M. Lienau
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Publication number: 20040264243Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height. In one embodiment, the wave induced into the sense line is a positive wave and represents a binary “1”. In another embodiment the wave induced into the sense line is a negative wave and represents a binary “O”.Type: ApplicationFiled: June 3, 2004Publication date: December 30, 2004Inventors: Richard M. Lienau, James Craig Stephenson
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Patent number: 6710624Abstract: A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating “write fatigue”. The invention provides an integrated circuit, comprising a programmable OR array (24), a programmable AND array (28), coupled to the programmable OR array, and a macrocell output circuit (22).Type: GrantFiled: September 18, 2002Date of Patent: March 23, 2004Inventor: Richard M. Lienau
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Patent number: 6711069Abstract: The invention generally related to registers or flip-flop circuits. More particularly, the present invention refers to the use of non-volatile ferromagnetic memory cell to store binary data in a register or flip-flop circuit. It is an advantage of the invention to have a flip-flop with a ferromagnetic memory cell or bit to store data even when there is no power provided to the circuitry. Thus, saving power during operation of any associated circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, or eliminating “write fatigue”.Type: GrantFiled: September 19, 2002Date of Patent: March 23, 2004Inventor: Richard M. Lienau
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Patent number: 6680877Abstract: A solar counter to provide an accurate way of measuring the middle of the night or another selected fraction of the day or night. The solar counter activates an electronic event when it has finished counting down. For example, a lamp can be turned off half way through the dark part of the night. This process is extremely accurate, and adaptations of this concept can be used in the safety industry, irrigation, or in agriculture. One embodiment of this concept has a battery back-up circuit, but a substitute 50/60 Hz clock input frequency in the case of AC power loss can also be provided using an uninterruptible power supply (UPS).Type: GrantFiled: January 24, 2003Date of Patent: January 20, 2004Inventor: Richard M. Lienau
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Publication number: 20030223265Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).Type: ApplicationFiled: September 20, 2002Publication date: December 4, 2003Inventor: Richard M. Lienau
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Publication number: 20030222675Abstract: A programmable array logic circuit macrocell using ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data. It is an advantage of the invention to have the ferromagnetic memory cells or bits to store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shutdown. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein, thus eliminating “write fatigue”. The invention provides an integrated circuit, comprising a programmable OR array (24), a programmable AND array (28), coupled to the programmable OR array, and a macrocell output circuit (22).Type: ApplicationFiled: September 18, 2002Publication date: December 4, 2003Inventor: Richard M Lienau
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Publication number: 20030222676Abstract: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line.Type: ApplicationFiled: September 19, 2002Publication date: December 4, 2003Inventor: Richard M. Lienau