Abstract: A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.

Abstract: A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.

Abstract: A clock system is provided capable of using an external system clock for driving at least one charge circuit of a semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system, in one embodiment, includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.

Abstract: Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

Abstract: A complete solution to block noise from eDRAM macro to the analog core, and vice verse, in a system-on-chip IC design. Specifically, there is provided a first isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a DC generator circuit fabricated therein; and, a second isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a noise sense amplifier bank and DRAM arrays fabricated therein. A power supply source is provided for supplying power to each DC generator circuit, noise sense amplifier bank and DRAM array; as is a power bus for providing power and a separate power bus for providing a ground to each of the DC generator circuit, and the noise sense amplifier circuit and DRAM array components. In this manner, noise contamination with noise sensitive devices in said IC is reduced and, further noise contamination of the DRAM array as sourced from the IC is reduced.

Abstract: Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

Abstract: A voltage regulator for DRAM chips having known short duration high current load events started by a trigger signal includes a regulating transistor operating in the weak inversion mode and a boost driver circuit. The trigger signal that starts the load event also triggers the boost driver circuit to produce a shaped boost signal at the correct time. The boost signal is applied to the gate of the regulating transistor to counteract the expected voltage drop at the output of the regulating transistor. The expected voltage drop is due to the known characteristics of the regulating transistor which include a change in threshold voltage of the regulating transistor during the high current flow of the load event. A switch device disconnects a preregulator during the load event and reconnects the preregulator thereafter. The boost signal is preferably applied to the regulating transistor through a capacitive divider.

Abstract: An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir stores a boost voltage under the control of a charge pump that is regulated by a voltage regulator. One of the local word lines coupled to a selected master word line is enabled by a driver that receives the boost voltage. The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.