Abstract: Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.

Abstract: One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.

Abstract: One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.

Abstract: Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.

Abstract: The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device (50) includes a transmit serializer (16), a transmit output buffer (13), a first phase interpolator (52), a phase locked loop (42), a second phase interpolator (44), a receive deserializer (18), a receive input buffer (15), and phase adjust logic (46). The PLL (42) generates a timing signal in accordance with a reference clock signal (43). In one mode of operation, the transmit serializer (16) transmits data for output through the transmit output buffer (13) in accordance with the timing signal generated by the PLL (42). In another mode of operation, the phase interpolator (52) accepts as input the timing signal generated by the PLL (42).