Abstract: A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

Abstract: A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

Abstract: A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.

Abstract: A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

Abstract: A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system memory particularly when the primary memory could include memory types where the write operation mixes non-data with data.

Abstract: A system and method are provided for bypassing cache memory when reading data from system memory particularly when the primary memory could include memory types where the read operation mixes non-data with data. A system and method are provided for bypassing and invalidating cache memory when writing data to system memory particularly when the primary memory could include memory types where the write operation mixes non-data with data.

Abstract: An over-voltage protection circuit is disclosed herein for protection against over-voltage of an energy storage device while charging. The circuit operates within the operational limits of a battery-operated device, such as a mobile or handheld device. The over-voltage protection circuit comprises an over-voltage protection device, and an over-voltage protection controller. The controller allows current to flow to the over-voltage protection device only when an energy storage device is experiencing over-voltage.

Abstract: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.

Abstract: A system and method of creating and managing encryption keys in a data processing device generates subsequent encryption keys by combining the existing encryption key with an existing password and seed value. In the preferred embodiment, the initial encryption key is embedded during manufacture and is unknown to the user and manufacturer, thus ensuring that all subsequent encryption keys are derived from an unknown value. When a subsequent encryption key is generated, all data encrypted using the existing encryption key is decrypted using the existing encryption key and re-encrypted using the subsequent encryption key before the existing encryption key is overwritten. In a further aspect, during encryption/decryption the encryption key is combined with the sector address of the data to be encrypted/decrypted in order to generate a unique key for each sector of data to be encrypted/decrypted.

Abstract: The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted.

Abstract: A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor.

Abstract: A device employs a method for determining the data bus width of a non-volatile memory, such as NAND flash memory. The method performs at least two read operations on the non-volatile memory so as to test the changing of selected data bits. The method may be performed such that weak pull down and pull up operations are performed to test the data outputs of the non-volatile memory.

Abstract: A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.

Abstract: A boot method an apparatus arc described which reduce the likelihood of a security breach in a mobile device, preferably in a situation where a reset has been initiated. A predetermined security value, or password, is stored, for example in BootROM. A value of a security location within FLASH memory is read and the two values are compared. Polling of the serial port is selectively performed, depending on the result of such comparison. In a presently preferred embodiment, if the value in the security location matches the predetermined security value, then polling of the serial port is nut performed. This reduces potential security breaches caused in conventional arrangements where code may be downloaded from the serial port and executed, which allows anyone to access and upload programs and data in the FLASH memory, including confidential and proprietary information.

Abstract: A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.

Abstract: A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.