Abstract: A signal processing device includes a filter, configured to receive first data representing a signal for wireless transmission, modify the first data in a filter operation, and output second data as the modified first data; a peak detector, configured to detect third data representing a peak of the signal, wherein the third data are a subset of the first data; a signal canceller, configured to receive the third data and to generate fourth data representing a cancellation signal corresponding to the peak of the signal; and a peak modifier, configured to receive the second data and the fourth data, and to generate fifth data using the second data and the fourth data, wherein the fifth data represent the signal with a modified peak.

Abstract: A system is provided, a circuitry comprising a plurality of processing elements (PEs) and configured to receive as input entries of a Hermitian positive-definite matrix A. The circuitry is also configured to Cholesky decompose the matrix A by deriving an intermediate numerator for at least one of the entries. The circuitry is additionally configured to calculate a square root for the intermediate numerator and to derive as an output an entry of a lower triangular matrix L based on the square root, wherein A=LL*, and wherein L* is a conjugate transpose of the lower triangular matrix L.

Abstract: The present invention provides a mobility device and methods of use to easily and quickly transfer a physically challenged individual from one seat to another seat. The mobility device and methods of use of the present invention also facilitates moving the physically challenged individual from one seat located at one location to another seat located at another location.

Abstract: Techniques and mechanisms provide a technique for compression using an approximation of a mu-law algorithm.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: Techniques and mechanisms provide a technique for compression using an approximation of a mu-law algorithm.

Abstract: A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude correction to the signal based on the characteristics of the passband filter. A filter group delay predistorter may also be employed to correct group delay variation introduced by the narrow passband filter.

Abstract: Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals.

Abstract: A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude correction to the signal based on the characteristics of the passband filter. A filter group delay predistorter may also be employed to correct group delay variation introduced by the narrow passband filter.

Abstract: A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude correction to the signal based on the characteristics of the passband filter. A filter group delay predistorter may also be employed to correct group delay variation introduced by the narrow passband filter.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: A digital predistorter for improving the performance of a narrow passband filter near the output is disclosed. The digital predistorter provides amplitude correction to the signal based on the characteristics of the passband filter. A filter group delay predistorter may also be employed to correct group delay variation introduced by the narrow passband filter.