Patents by Inventor Richard Malinowski

Richard Malinowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9945672
    Abstract: A system for providing destination guidance based on tracked real-time ambient health conditions includes one or more location tracking devices carried by one or more participants. The one or more location tracking devices track the locations of the one or more participants and providing the tracked locations to a central server when it is determined that the one or more participants are infected by a communicable ailment. The central server receives the provided tracked locations and transmits the tracked locations to a navigation guidance device carried by a user, without transmitting identifying details about the one or more participants. The navigation guidance device carried by the user provides guidance to the user on selecting a destination or route that avoids contact with or exposure to the plurality of participants.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Swaminathan Balasubramanian, Thomas G. Lawless, III, Jason Richard Malinowski, Cheranellore Vasudevan
  • Publication number: 20170350702
    Abstract: A system for providing destination guidance based on tracked real-time ambient health conditions includes one or more location tracking devices carried by one or more participants. The one or more location tracking devices track the locations of the one or more participants and providing the tracked locations to a central server when it is determined that the one or more participants are infected by a communicable ailment. The central server receives the provided tracked locations and transmits the tracked locations to a navigation guidance device carried by a user, without transmitting identifying details about the one or more participants. The navigation guidance device carried by the user provides guidance to the user on selecting a destination or route that avoids contact with or exposure to the plurality of participants.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: SWAMINATHAN BALASUBRAMANIAN, THOMAS G. LAWLESS, III, JASON RICHARD MALINOWSKI, CHERANELLORE VASUDEVAN
  • Patent number: 8756669
    Abstract: A system and method of implementing a security mode in a mobile communications device, including a mobile communications device comprising a processor, and a computer readable storage medium storing programming for execution by the processor, the programming including instructions to activate a security mode of the mobile communications device, and pursuant to activation of the security mode, disable a first class of features of the mobile communications device, wherein other features of the mobile communications device remain enabled after activation of the mobile security.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 17, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventor: Richard Malinowski
  • Publication number: 20130347084
    Abstract: A system and method of implementing a security mode in a mobile communications device, including a mobile communications device comprising a processor, and a computer readable storage medium storing programming for execution by the processor, the programming including instructions to activate a security mode of the mobile communications device, and pursuant to activation of the security mode, disable a first class of features of the mobile communications device, wherein other features of the mobile communications device remain enabled after activation of the mobile security.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventor: Richard Malinowski
  • Patent number: 6148380
    Abstract: An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: November 14, 2000
    Assignee: Intel Corporation
    Inventors: James M. Dodd, Richard Malinowski
  • Patent number: 6044441
    Abstract: A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator. The invalid pattern comparator operates to compare the tag address with an invalid pattern. A qualifier unit is coupled to the address comparator and the invalid pattern comparator. The qualifier unit outputs a signal when the address to be accessed in the memory matches the tag address in the address tag and the address tag does not match the invalid pattern.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventor: Richard Malinowski
  • Patent number: 6000017
    Abstract: A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: December 7, 1999
    Assignee: Intel Corporation
    Inventors: George Hayek, Richard Malinowski
  • Patent number: 5603010
    Abstract: A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: February 11, 1997
    Assignee: Intel Corporation
    Inventors: James M. Dodd, Richard Malinowski, Brian K. Langendorf, George R. Hayek
  • Patent number: 5553023
    Abstract: This invention relates to an improved memory storage system which allows selective ranges of memory locations, which can also be referred to as virtual memory banks, to be enabled and disabled. The ranges of memory locations can be disabled to avoid refreshing unused memory location and to eliminate faulty memory locations. Also, the ranges of memory locations can be treated as blocks or banks of memory regardless of the physical chips used to store the data. In other words, if a memory bank has a capacity of 16 MB, the range of memory locations may be a portion of the total capacity of this memory bank, for example 8 MB or 4 MB, and the remainder of the memory bank can be unaffected or be the subject of another range of memory locations. In a preferred embodiment, the ranges of memory locations is at least 2 MB in size.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: September 3, 1996
    Assignee: LSI Logic Corporation
    Inventors: Winnie K. W. Lau, Richard Malinowski
  • Patent number: 4918353
    Abstract: This invention relates to a glass reflector and tungsten-halogen lamp combination wherein the lamp is cemented into the glass reflector with an aluminum phosphate cement composition which comprise a mixture of aluminum phosphate containing excess phosphoric acid, relatively small particle size alumina and a mixture of relatively medium and coarse particle size inert filler materials and wherein the lamp contains a hermetic seal between quartz and a molybdenum foil with that portion of the foil in the seal area which is exposed to an oxidizing environment coated with alkali metal silicate.
    Type: Grant
    Filed: June 13, 1989
    Date of Patent: April 17, 1990
    Assignee: General Electric Company
    Inventors: Clark D. Nelson, Richard Malinowski, Catherine Mers, Diana Essock, Vito Arsena, Mary Jaffe