Abstract: A server computing device can determine if a software application executing on a client computing device has not been tampered. Software executes on the server device and communicates either directly or indirectly with an attestation service; a client software application running on the client computing device communicates with the same attestation service. A client software application that is able to calculate a cryptographic hash fingerprint of its executing code image communicates to the attestation service to prove it is untampered with. The attestation service then generates a pass or fail attestation result. The attestation result is communicated between the attestation service and the server computing device. The behaviour of the server computing device is controlled in a way that is conditional on whether a prior attestation of the client software was a pass or fail attestation result.

Abstract: A server computing device can determine if a software application executing on a client computing device has not been tampered. Software executes on the server device and communicates either directly or indirectly with an attestation service; a client software application running on the client computing device communicates with the same attestation service. A client software application that is able to calculate a cryptographic hash fingerprint of its executing code image communicates to the attestation service to prove it is untampered with. The attestation service then generates a pass or fail attestation result. The attestation result is communicated between the attestation service and the server computing device. The behaviour of the server computing device is controlled in a way that is conditional on whether a prior attestation of the client software was a pass or fail attestation result.

Abstract: A low overhead mechanism for supporting speculative execution and code compression in a Very Long Instruction Word (VLIW) microprocessor. Profitable speculations can be determined statically at compile time and a low overhead hardware recovery mechanism used that does not require compensation code.

Abstract: A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular application. Executable code for another microprocessor type is translated into the specialized instruction set of the configured microprocessor. The configured microprocessor may then be used as a coprocessor in a system containing another microprocessor running the original executable code.

Abstract: An automatic process for configuring a microprocessor architecture that consists of a number of execution units with configurable connectivity between them. The data and control flows within an input program are used to influence the process so that the resulting microprocessor is able to efficiently exploit parallelism available within the input program.

Abstract: A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.