Abstract: The invention relates to an integrated circuit comprising a succession of N identical elementary circuits (CE1, CE2, . . . CEN), juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. An upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and an upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. The integrated circuit is applicable to analog-digital converters or digital-analog converters with high resolution.

Abstract: The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of “flash” type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted Vep?Ven on two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pj of rank j of a first network and a tap P?N?j+1 of rank N?j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.

Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

Abstract: The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T1, T1b; T2, T2b), cascaded together, the second pair (T2, T2b) having complementary current outputs (H, Hb) that flip according to the states of the inputs (E, Eb). The first pair (T1, T1b) is connected to a ground (GND) through a current source, supplying a current of value Io and comprising a transistor (Ts1) biased by a voltage Vbias, and it is supplied by a voltage equal to N·Vbe+Vbias, where N is a whole number (preferably equal to 1) and Vbe is the base-emitter voltage of the transistor (Ts1). The second pair (T2, T2b) is connected to ground directly through a resistance (R2). The invention can be applied to the on-off control of sample-and-hold circuits, multiplexers, fast low-voltage logic circuits, etc.

Abstract: The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E?) and a respective differential output (S, S?). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T1a, T1a?) powered by a voltage tapped off from the terminals of the storage capacitor (C?, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca?) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T2a, T3a, SC1a; T2?a, T3?a, SC1a?) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.

Abstract: The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T1, T1b; T2, T2b), cascaded together, the second pair (T2, T2b) having complementary current outputs (H, Hb) that flip according to the states of the inputs (E, Eb). The first pair (T1, T1b) is connected to a ground (GND) through a current source, supplying a current of value Io and comprising a transistor (Ts1) biased by a voltage Vbias, and it is supplied by a voltage equal to N·Vbe+Vbias, where N is a whole number (preferably equal to 1) and Vbe is the base-emitter voltage of the transistor (Ts1). The second pair (T2, T2b) is connected to ground directly through a resistance (R2). The invention can be applied to the on-off control of sample-and-hold circuits, multiplexers, fast low-voltage logic circuits, etc.

Abstract: The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Io and the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The resistor network is supplied by a variable reference voltage originating from a servoloop circuit which locks the voltage level of the middle of the resistor network at a voltage equal to the common mode voltage (VS?VSN)/2 present at the output of the sample-and-hold module.

Abstract: The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

Abstract: The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

Abstract: The invention relates to the fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. In order to minimize the influence of parasitic capacitances of the resistor network on the comparator response time, it is provided that the series resistor network receives a reference voltage (VH) and is traversed by a fixed current I0 and that the row i (i varying from 1 to N) comparator (COMPi) essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The dual differential amplifier supplies a voltage representing a difference of the form (VS?VSN)?(N?2i)r.

Abstract: The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E?) and a respective differential output (S, S?). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T1a, T1a?) powered by a voltage tapped off from the terminals of the storage capacitor (C?, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca?) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T2a, T3a, SC1a; T2?a, T3?a, SC1a?) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.

Abstract: Front-ends for CCD cameras are known which use a clamping part and a sampling part using parallel arrangement of a coil and a resistor. As coils are almost always bulky they can not be integrated.

Abstract: The invention relates to an interface circuit FE intended to receive a pseudo-periodical input signal Vin having a reference level and a video level, and to supply a signal Vs having a level which is representative of the difference between the reference level and the video level, said interface circuit comprising: two sampling branches BR1 and BR2 simultaneously supplying the reference level and the video level, and a subtracter SUB having inputs which receive the outputs of the branches BR1 and BR2. According to the invention, the inputs of the branches BR1 and BR2 are jointly connected via a first capacitance C1 to the input of the interface circuit FE, which comprises control means CM allowing adjustment of the values of the signals at the inputs of the subtracter SUB so that they are equal when they are representative of one and the same reference level.

Abstract: An A/D conversion device, for converting an analog input voltage Vin into a digital output signal encoded in N bits OUT(0:N-1), includes a first decoder (FNE) for generating the least significant bits OUT(0:K) of the output signal, and a second decoder (CRS) for generating signals which are representative of transitions to which the most significant bits OUT(i+1) of the output signal are to be submitted, for i=k to N-2. Each transition of the bit OUT(i+1) is signaled by signals referred to as antecedent signals A(i+1) and subsequent signals P(i+1), while an encoder (ENC) is provided for synchronizing each transition with a transition of the bit OUT(i) of the next lower weight.

Abstract: An A/D conversion device includes: an amplifier AMP provided with regulating means controlled by a control signal OC or GC for adjusting the value of its output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into digital signals.The device includes means S0 or MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALOS or CALG is active, and at least a calibration arrangement DEC0 or DECM each havinga module comparing the output of the second converter ADC2 with a predetermined binary word,a module supplying the control signal OC or GC whose value depends on the result of said comparison, andmeans for storing the control signal OC or GC when the corresponding calibration signal CALOS or CALG is inactive.

Abstract: An A/D conversion device includes:an amplifier AMP receiving an input voltage V1 and supplying an output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into a digital signal by comparing it with reference voltages generated by a resistance ladder R2 traversed by a bias current.The device includes a multiplexer MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALG is active, and a calibration arrangement DECM which compares the output of the second converter ADC2 with a predetermined binary word, supplies a control signal GC, which depends on the result of said comparison and determines the value of the bias current, and stores the control signal GC when the calibration signal CALG is inactive.

Abstract: An amplifying device has a decibel gain that evolves quasi-linearly as a function of the digital value of a control word C(O:M-1). The device includes: an amplifying stage with K amplifiers having mutually different decibel gains, the gain in decibels of each amplifier being a multiple of the same value G0; a switching stage with K switches; a gain-controlled amplifier having a gain which varies between 0 and G0 as a function of the value of the N least significant bits (C(O:N-1)) of the control word received at its digital input; and a decoder receiving a digital word including the (M-N) most significant bits (C(N:M-1)) of the control word. The decoder has K logic outputs controlling the K switches.

Abstract: The invention relates to a digitally gain-controlled amplifier including a transconductance stage provided with means for producing, at each of its N current outputs, a current (Itr) having a variable component which is representative of the analog input voltage. The amplifier also includes a switching stage comprising N switches each controlling the activation or deactivation of one of the N current outputs of the transconductance stage. Finally, the amplifier has a current/voltage conversion stage having one voltage output constituting the analog output of the amplifier and supplying a voltage which is representative of the currents received at its N current inputs.

Abstract: An A/D converter in which an interpolation circuit (15, 16, 17, 18) makes weighted combinations of reference crossing signals (A/Ac,B/Bc) provided by an input circuit (100, 200), so as to obtain an expanded set of reference crossing signals (A/Ac+A1/Ac1 . . . A7/Ac7, B/Bc+B1/Bc1 . . . Bc7). The interpolation circuit (15, 16, 17, 18) is arranged to make at least one weighted combination of reference crossing signals with weighting factors which have a non-integer ratio so as to compensate for a non-linearity in the reference crossing signals (A/Ac,B/Bc). Accordingly, a better compromise is obtained between accuracy, on the one hand, and circuit complexity, on the other hand.