Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A storage device includes: a host interface to receive a host command from a host device over a storage interface; one or more memory translation layers to execute one or more operations associated with the host command to retrieve one or more chunks of data associated with the host command from storage memory; a bitmap circuit including a bitmap to track a constrained order of the one or more chunks of data to be transferred to the host device; and a transfer trigger to trigger a data transfer to the host device for the one or more chunks of data in the constrained order according to a state of one or more bits of the bitmap.

Abstract: A storage device includes: one or more logical blocks to store host data received from a host device, the logical blocks having a logical block address (LBA); an LBA range table to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and an overlap check circuit to compare an LBA range associated with an active request with the one or more LBA ranges associated with the one or more commands, and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A storage device includes: one or more logical blocks to store host data received from a host device, the logical blocks having a logical block address (LBA); an LBA range table to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and an overlap check circuit to compare an LBA range associated with an active request with the one or more LBA ranges associated with the one or more commands, and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: A storage device includes: a host interface to receive a host command from a host device over a storage interface; one or more memory translation layers to execute one or more operations associated with the host command to retrieve one or more chunks of data associated with the host command from storage memory; a bitmap circuit including a bitmap to track a constrained order of the one or more chunks of data to be transferred to the host device; and a transfer trigger to trigger a data transfer to the host device for the one or more chunks of data in the constrained order according to a state of one or more bits of the bitmap.

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.

Abstract: This invention provides an improved means for communicating between a central communications or computer processor and a plurality of peripheral devices via a serial interface such as a pulse coded modulation (PCM) bus. The processor sends data via one of two redundant communications channels, such as a PCM bus, to the peripheral devices, each of which is equipped with a data receiving means such as a shift register. These data receiving means check a specific character position of the input data for a pattern which is unlikely to occur at random, such as hexadecimal `7E`. (X `7E` has a bit pattern of 0111 1110.) Whenever the specified pattern is detected, a return pattern is generated in a specified character position of the data stream which is periodically sent back to the processor. As long as these return characters are received, the processor continues to send data via the first communications channel, and the receiving peripheral devices continue to read their data from that channel.

Abstract: An apparatus for alternate memory addressing of a random access memory (RAM) allows a first processor to write into the memory on a row-by-row basis and a second processor to read out of the memory on a column-by-column basis. The memory is typically divided into a pluralilty of channels into which the first processor writes data for respective channels asynchronously by the use of twin RAMs. While one RAM is written to by the first processor, the second RAM is read from synchronously with automatic address translation.

Abstract: A digital voice recording and reproducing device, preferably connected to a telephone network uses a storage RAM to store voice messages and digital signals. An internal processor connected to the storage RAM processes digital signals to and from the storage RAM. A high speed RAM connected to the internal processor receives and transmits digital signals to and from the internal processor. Encoders and decoders encode voice signals into pulse code modulated (PCM) signals to be delivered into the high speed RAM, and decode digital PCM signals from the high speed RAM. A high speed processor (HSP) connected to the high speed RAM delivers signals from a switch to the high speed RAM.