Abstract: A method for making semiconductor devices such as dynamic read/write memory cell arrays of the one-transistor N- channel silicon gate type employs an ion implant of high dosage to produce N+ source/drain regions. The transistor and capacitor gates are in place when this implant is performed, and the chain oxide beneath the gates can break down due to static charge produced on the slice surface as a result of the ion implant. To prevent build-up of static charge on the surface, a thin coating of polysilicon is applied before the implant and grounded. This coating is subsequently removed by thermal oxidation or etching. Alternatively, a thermal oxide coating may be used as it will prevent the implanted arsenic from reaching the polysilicon gates, although it will penetrate a thinner thermal oxide coating over the source/drain area. Other dielectric films such as silicon nitride may also be used.