Patents by Inventor Richard N. Pelavin

Richard N. Pelavin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140344323
    Abstract: An electronic system is provided for facilitating configuration management of a service or application distributed over a plurality of nodes that can be in single datacenter or network or span multiple ones The system includes a receiver for receiving a system model, a reasoner, and a workflow engine. The reasoner automatically processes the system model received by the receiver to produce an executable plan for the distributed service. The workflow engine includes a temporal sequencer for dispatching commands to the nodes to carry out the executable plan in a temporally coordinated manner, thereby providing the distributed service. Also provided is a method for facilitating configuration management of a distributed service.
    Type: Application
    Filed: March 17, 2014
    Publication date: November 20, 2014
    Applicant: Reactor8 Inc.
    Inventors: Richard N. Pelavin, Nate D'Amico
  • Patent number: 7484004
    Abstract: Methods are described for analyzing access list subsumption in routing devices of a computer network and for identifying computer network integrity violations, by producing structured data that includes stored router names and access lists that include elements with address/mask pairs, or patterns used to filter data into and out of a routing device, respectively; determining whether access lists in the structured data include elements in which a first element in the access list has a more general or equal address/mask pair, or pattern, respectively, than a second or subsequent element, or pattern; and storing in electronic memory a report of elements or a list of patterns, respectively, in which a first element or pattern is more general than or equal to a second or subsequent element or pattern.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: January 27, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Richard N. Pelavin, James G. McGuire, Herbert S. Madan
  • Patent number: 6883034
    Abstract: Methods are described for analyzing access list subsumption in routing devices of a computer network and for identifying computer network integrity violations, by producing structured data that includes stored router names and access lists that include elements with address/mask pairs, or patterns used to filter data into and out of a routing device, respectively; determining whether access lists in the structured data include elements in which a first element in the access list has a more general or equal address/mask pair, or pattern, respectively, than a second or subsequent element, or pattern; and storing in electronic memory a report of elements or a list of patterns, respectively, in which a first element or pattern is more general than or equal to a second or subsequent element or pattern.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: April 19, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Richard N. Pelavin, James G. McGuire, Herbert S. Madan
  • Patent number: 6393486
    Abstract: A method is provided for managing a computer network includes the step of providing respective router configuration information in executable form; producing respective Structured Router Objects (SROs) that are respectively associated with respective router configuration information and that respectively organize associated information in executable form in respective structures in electronic memory; and producing respective Single Protocol Topology (SPT) objects in electronic memory, each respectively associated with a different respective single protocol and each respectively interrelating SROs associated with the same respective single protocol.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: May 21, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Richard N. Pelavin, James G. McGuire, Herbert S. Madan
  • Patent number: 4593363
    Abstract: For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.
    Type: Grant
    Filed: August 12, 1983
    Date of Patent: June 3, 1986
    Assignee: International Business Machines Corporation
    Inventors: Michael Burstein, Se J. Hong, Richard N. Pelavin