Patents by Inventor Richard N. Woolley

Richard N. Woolley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8549342
    Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 1, 2013
    Assignee: Marvell International Ltd.
    Inventors: Roy G. Moss, Douglas G. Keithley, Richard N. Woolley
  • Patent number: 7925912
    Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 12, 2011
    Assignee: Marvell International Ltd.
    Inventors: Roy G. Moss, Douglas G. Keithley, Richard N. Woolley
  • Patent number: 4564941
    Abstract: The present invention provides methods and apparatus for improved error detection in a data processing system. The techniques of the present invention insure that there is a high probability that an error in a record of data (each record comprising a plurality of data bits) is detected. In the event of an error, the present invention applies a randomizing function to the error which modifies subsequent bits within the record and then propagates and further randomizes the error throughout the record to magnify its apparent size. The randomizing and propagation of the error significantly lowers the misdetection probability for random errors within a record, in that error detectability is no longer pattern sensitive. The use of both propagation and randomization functions significantly alters the data containing an error, such that a high probability of detection using check-sum techniques exists.
    Type: Grant
    Filed: December 8, 1983
    Date of Patent: January 14, 1986
    Assignee: Apple Computer, Inc.
    Inventors: Richard N. Woolley, Neal Glover, Richard Williams