Abstract: An improved automatic placement process for placing logic cells in a universal array. Unused basic units are assigned to rows to reduce the congestion of the wiring in high congestion regions of a universal array. These assigned unused basic units are allocated among rows in a pyramidal manner. Those unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion. During a pair exchange portion of the placement process, quality criteria used for deciding whether to exchange two logic cells on different rows include skipped rows in a node, y-span of a node, minimizing the number of logic cells in excess of two in a node on a row, making a longest row shorter and making longer a shortest row or one which is within a tolerance of being a shortest row.

Abstract: A routing process for automatic computer aided routing of customizing conductors in a universal array which has a single customizing conductive layer is improved by executing a pathfinding routing process for conductors which connect pins on the same row before routing other conductor types. Routing of conductors which connect a pin on the side surface to a pin in the basic unit row region is improved by initially restricting permissible routes to be within a set of three contiguous rectangles. Routing opportunities for potentially failed conductors are increased by allowing customizing conductors to extend parallel to the length of the basic unit rows in the region between adjacent tunnel ranks in the final routing step. An improved custom IC results.The conductor number of the shortest and the longest conductor in each class is stored separately from the routing grid matrix so that these numbers can be directly retrieved as needed.

Abstract: A routing method implemented in the stored programs of a digital computer ich is programmably operated to generate the wire interconnect masks for a two level metallization automated universal array having undefined roadbeds between rows of cells comprised of identical semiconductor device basic units which are further interconnected to provide a particular integrated circuit structure. Conductor routing is provided by a computer aided design system that, among other things, carries out a route analysis process which determines in which roadbed each wire should be tentatively routed in conjunction with generating a routing density profile for minimizing congestion for a particular circuit design and when the roadbed density is exceeded, certain wires are removed under a set of criteria for routing by a pathfinder routing process.

Abstract: A computer process for the automatic layout of a multiport, two-dimensional icrocircuit. The program provides for improved cell placement and power distribution while minimizing the overall chip area dimensions. The power distribution layout provides for the supply of power to cell rows which is independent of the peripheral power routes.

Abstract: A universal array of the type designed for automatic computer aided design of its customizing conductive layer is easily scaled to change the number of devices in the array. The array comprises an inner region having first direction extending rows of originally uncommitted device cells. Each row of cells is powered from first direction extending row power buses. These rows of cells are spaced apart in a second, perpendicular, direction by interleaved first type wiring corridors. The inner region is surrounded by an outer region including second type wiring corridors and peripheral cells. The second type wiring corridors space at least some peripheral cells from the inner region. The second type corridors include second-direction-extending inner-region-supplying power buses which connect to cell row power buses and wiring roadways spaced from the inner region by the inner buses. The wiring roadways are free of row power buses.

Abstract: A computer program for the fully automatic layout of hybrid microcircuits. he program, under certain options, guarantees one-hundred percent routing connectivity for components ranging from discretes to VLSI. Special features such as bottom-up or top-down routing, sequential level routing and user-defined grid spacing provide extensive design flexibility.

Abstract: A large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing.