Abstract: An electronic device includes a housing having a sidewall defining an internal volume, a display secured to the housing, a camera assembly disposed in the internal volume between the display and the sidewall, a spring finger biasing the camera assembly away from the sidewall, and a compression block disposed between the camera assembly and the sidewall.

Abstract: A recyclable fluid cleaning system wafers includes a cleaning vessel configured to clean semiconductor wafers immersed in a bath of persulfuric acid cleaning solution, the cleaning solution circulated through a primary process tool fluid path; a secondary fluid path that diverts a portion of the persulfuric acid cleaning solution for electrolysis treatment thereof; an electrolysis reactor within the secondary fluid path that receives oxidant depleted sulfuric acid, the electrolysis reactor having electrodes that, when activated causes sulfate ions in the solution to be oxidized and form persulfate ions that are recombined with fluid from the primary fluid path and fed back to the cleaning vessel; and one or more controller devices in operative communication with the cleaning vessel and with the electrolysis reactor.

Abstract: A method of implementing cleaning solution replacement in a recyclable fluid cleaning system for semiconductor wafers includes activating electrode current for an electrolysis reactor included in the cleaning system. At least one of electrode voltage and operating time for the electrolysis reactor is monitored, until a trigger point has been reached. The trigger point includes one of the electrode voltage reaching a predetermined threshold voltage value, a process time counter reaching a predetermined counter value, and a time value that the electrode voltage has been at the threshold voltage value reaching predetermined value. The process time counter is incremented based on one or more of actual wafer processing time, wafer type, number of wafers processed, and thickness of material to be stripped. Upon reaching the trigger point, the electrode current is deactivated, and at least a portion of cleaning system fluid is drained and replaced with fresh cleaning fluid.

Abstract: A recyclable fluid cleaning system wafers includes a cleaning vessel configured to clean semiconductor wafers immersed in a bath of persulfuric acid cleaning solution, the cleaning solution circulated through a primary process tool fluid path; a secondary fluid path that diverts a portion of the persulfuric acid cleaning solution for electrolysis treatment thereof; an electrolysis reactor within the secondary fluid path that receives oxidant depleted sulfuric acid, the electrolysis reactor having electrodes that, when activated causes sulfate ions in the solution to be oxidized and form persulfate ions that are recombined with fluid from the primary fluid path and fed back to the cleaning vessel; and one or more controller devices in operative communication with the cleaning vessel and with the electrolysis reactor.

Abstract: A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.

Abstract: A method of implementing cleaning solution replacement in a recyclable fluid cleaning system for semiconductor wafers includes activating electrode current for an electrolysis reactor included in the cleaning system. At least one of electrode voltage and operating time for the electrolysis reactor is monitored, until a trigger point has been reached. The trigger point includes one of the electrode voltage reaching a predetermined threshold voltage value, a process time counter reaching a predetermined counter value, and a time value that the electrode voltage has been at the threshold voltage value reaching predetermined value. The process time counter is incremented based on one or more of actual wafer processing time, wafer type, number of wafers processed, and thickness of material to be stripped. Upon reaching the trigger point, the electrode current is deactivated, and at least a portion of cleaning system fluid is drained and replaced with fresh cleaning fluid.

Abstract: In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Abstract: In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Abstract: An aqueous seeding solution of palladium acetate, acetic acid and chloride.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.

Abstract: A method for controlling the shape of copper features, having the following steps: