Patents by Inventor Richard Oed

Richard Oed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8543740
    Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Lars Lotzenburger, Richard Oed
  • Publication number: 20110202698
    Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.
    Type: Application
    Filed: January 20, 2011
    Publication date: August 18, 2011
    Applicant: Texas Instruments Deutschland GmbH
    Inventors: Lars Lotzenburger, Richard Oed
  • Patent number: 7002975
    Abstract: In a node failure detection technique at least one supervisory data processing node periodically transmits a receipt acknowledge data packet to each other data processing node. The supervisory data processing node determines a data processing node has failed upon failure to receive a return acknowledge data packet. This acknowledge data packet preferably includes health data concerning its current health operating status. The supervisory data processing node sends a reset data packet to any failed data processing node determined. If the reset does not return the data processing node to normal operation, then routing data at neighboring data processing nodes is altered to route data packets around the failed node.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: February 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Peter Galicki, Richard Oed
  • Patent number: 6470402
    Abstract: For the transfer of data coming from N channels, which are sampled in a pre-determined sequence, to a processor by means of a circular FIFO store (30) with n storage stages, whilst retaining this pre-determined sequence, and whereby the output of the last stage is connected to the input of the first stage, the following steps are implemented: a) With each write operation of data into the FIFO store (30), a write pointer (SZ) is set to a value which designates the storage stage into which has been written last; b) with each reading operation of data from the FIFO store (30), a read pointer (LZ) is set to a value which designates the storage stage which is subsequently to be read, whereby the reading process always comprises the reading of data from i×N storage stages, i being an integer and i×N<n; c) a trigger pointer (TZ) is set to a value j×N, j being an integer, j×N<n and i≦j; d) if, after a write process, the value of the write pointer (SZ) is equal to or greater than t
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Heinz-Peter Beckemeyer, Richard Oed, Manfred Christ
  • Publication number: 20020018480
    Abstract: In a node failure detection technique at least one supervisory data processing node periodically transmits a receipt acknowledge data packet to each other data processing node. The supervisory data processing node determines a data processing node has failed upon failure to receive a return acknowledge data packet. This acknowledge data packet preferably includes health data concerning its current health operating status. The supervisory data processing node sends a reset data packet to any failed data processing node determined. If the reset does not return the data processing node to normal operation, then routing data at neighboring data processing nodes is altered to route data packets around the failed node.
    Type: Application
    Filed: July 13, 2001
    Publication date: February 14, 2002
    Inventors: Peter Galicki, Richard Oed